crc method for a serial driver for fiscal cash register

[MRAB]

On 2017-03-16 00:08, Chris Angelico wrote:
> On Thu, Mar 16, 2017 at 9:31 AM, MRAB <python at mrabarnett.plus.com> wrote:
>>> 3.2. If the carry bit from S1 is 1, the MSB of S1 and LSB of S0 are
>>> inverted.
>>> Points 2 and 3 are executed for all bytes, included in the calculation of
>>> the CRC - from the first byte after BEG up to and including byte END.
>>> 4. TR is loaded with 0 and point 3 is executed
>>> 5. TR is loaded with 0 and point 3 is executed
>>> 6. Byte S1 is transmitted
>>> 7. Byte S0 is transmitted
>>>
>> [snip]
>> Step 3 is a little unclear.
>>
>> Step 3.1 says to shift TR, but step 3.2 says to check the carry bit after
>> shifting S1, which is zero initially, therefore the carry bit will be clear,
>> therefore S1 and S0 won't have any bits inverted and will stay zero.
>>
>
> I think probably "if the carry bit from TR is 1" would make this all
> make sense. Otherwise TR, which is the data payload, is completely
> ignored.
>
Hence the need for examples.