Parsing VHDL with python, where to start.

Wolfgang Grafen wolfgang.grafen at ericsson.com
Tue Jul 29 11:14:49 EDT 2008


Svenn Are Bjerkem schrieb:
> Hi again,
> 
> when I get far enough to parse the VHDL (which is not currently the
> fact, but I have to look at the work coming up downstream) I will have
> to put it into an internal data structure and then write some classes
> to handle the MVC between whatever data I have and the PyQt4 widget
> that is going to show the block diagram. I own the book "Rapig GUI
> Programming with Python and Qt" by Mark Summerfield and try to read up
> on the PyQt way of doing things as I try to make a plan for my
> application. I have been looking for possible data structures with
> google just to find out that most of the ideas are stored in
> proceedings or to conferences or ieee papers not generally available
> to me. Is anybody experienced with designing data structures willing
> to share some ideas with me? Since I am using the open-source version
> of PyQt4, any information will eventually be available to public (if
> the app pass the planning stage) if that makes helping out any
> easier: :-) There is already an app called Qucs that is running in
> Qt-3 and being ported to Qt-4 that is written in C++, but I don't know
> how wise it is to just reverse-engineering C++ classes and translate
> them into python classes.

For me it is not very clear what you intend to do. After years of 
parsing parts of VHDL from time to time the rapid parsing way for me is 
using regular expressions instead of one of the parser frame works 
because of following reasons:

- It is hard for me to understand those frameworks
- They are very slow
- It is too much work for me to bring them up to work in a sensible way
- Compared with regular expression matching they usually need a lot of 
extra work.

Regular expressions work very well once the validation of the VHDL code 
was done by one of the commercial compilers.

Once you can rely on the code that it is valid VHDL
- Parse it with a regular expression for simple VHDL structures or
- Extract a structure first and analyse that with a set of regular 
expressions

The result can be stored into a combination of lists and dictionaries, 
dependend on the problem.

For processing with other tools the results could be stored into XML 
structures.

PyQt as a widget framework is not useful until here, but of course you 
could display your results in arbitrary graphical ways with PyQt, if you 
rally need to. You should know, printing out an ASCII or XML 
representation is so much more easy and quicker to code so I always 
prefer that. There are even editors/visualizers ready to display XML...

Best regards

Wolfgang



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