why did these companies choose Tcl over Python

[VernM]

On Oct 30, 1:25 pm, chewie54 <dfabrizi... at gmail.com> wrote:
> Hello,
>
> As an electronics engineer I use some very expensive EDA CAD tool
> programs that are scriptable using Tcl.  I was wondering why these
> companies have choose to use Tcl instead of Python.   Some of these
> are:
>
>    Mentor Graphics ModelTech VHDL and Verilog simulator
>    Synopsys  Design Compiler and Primetime Static Timing Analyzer
>    Actel FPGA tools.
>
> Tcl seems to very popular in my business as the scripting language of
> choice.
>
> I'm in the process of deciding to use Tcl or Python for a CAD tool
> program that I have been working on.    Most of the core of the
> program,  the database,   will be done is C as an extension to either
> Tcl or Python,   but I intend to use Tk or wxPthon for the GUI.   I do
> need publishing quality outputs from drawings done on a graphics
> device that are scaled to standard printer paper sizes.
>
> I would prefer to use Python but can't deny how popular Tcl is,  as
> mentioned above,  so my question is why wasn't Python selected by
> these companies as the choice of scripting languages for their
> product?
>
> Are there any obvious advantages like:
>
>     performance,
>     memory footprint,
>     better cross-platform support,
>     ease of use,
>
> Thanks in advance for your thoughts about this.

I'm an electrical engineer too, and have lamented the same lack of
Python scripting for tools like the ModelTech VHDL simulator. I think
the original choice had to do with with the ease of embedding TCL into
applications written in C, and the use of TCL in university EE
departments. I would rather die than try to write anything approaching
a complete application in TCL. Other braver souls have actually done
it, but I am sure they are masochists.

About a year ago I discovered an interesting project that embedded
Python in TCL (!).  it's called TCLPython. I have tried this out with
ModelSim 6.2, and it actually works! I have written a few Python
scripts that drive a signal in a VHDL simulation.

Here is a link: http://www.ellogon.org/petasis/index.php?option=com_content&task=view&id=27&Itemid=43

Best regards, Vern Muhr