Crashing IDLE

David LeBlanc whisper at oz.net
Thu May 30 22:24:06 EDT 2002


> -----Original Message-----
> From: python-list-admin at python.org
> [mailto:python-list-admin at python.org]On Behalf Of Peter Hansen
> Sent: Thursday, May 30, 2002 16:15
> To: python-list at python.org
> Subject: Re: Crashing IDLE
>
>
> Gustavo Cordova wrote:
> >
> > David LeBlanc wrote:
> > > "NOP" at the assembly language level does all those things! Events and
> > > interrupts are generally sensed at instruction/statement
> boundaries, and
> > > "pass" would (or should!) count as such. Methinks at a higher level of
> > > abstraction (but not really), the pcode interpreter loop
> > > should be doing
> > > this too.
> >
> > Woops, you are so right, and me and my big mouth should keep quiet.
> [snip]
> > pd: Isn't it "halt" which does all those things?
> >     My Z80 knowledge is becoming hazy...
>
> Instructions like HALT simply put the CPU into a state where
> *all* it does is sit and check for interrupts, and sometimes
> bump timer registers along.  It is in suspended animation,
> not reading or writing memory or incrementing the program
> counter.

"HALT" is often implemented as a "jump to self" in the chip's microcode.
This is a simple way of taking it through the microcode
sense/dispatch/process loop that is the basis of all macro ("regular")
instructions.

> Instruction NOP is a "live" instruction which executes just
> like any other instruction except that it leaves no side effects
> of any kind except an increase in the program counter and a
> small time delay (a couple of clock cycles).  It does not,
> however, *prevent* checking for interrupts which is always
> done (when they're enabled) after each instruction.
>
> Of course, with the gazillion different chips out there, I'm
> sure there are some that do things a little different, but
> these two are generally similar (if present) on all typical
> micros.

I really meant assembler as an analogy - Python's VM (interpreter if you
prefer) is quite analgous to a CPU with C as the microcode for the
underlying "simple" CPU. Too bad none of the user microcodable chips ever
made it into production/broadspread use. It would be interesting to create a
truly microcoded Python chip. Perhaps one of those 200,000 gate FPLA's....
hmmmmmmm.

> -Peter


David LeBlanc
Seattle, WA USA






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