[Python-Dev] Rattlesnake progress

[Gustavo Cordova]

> 
> It's also *much* harder to model the cache hierarchy properly so that 
> you can make sure they'd fit in the l1 cache, than it is to make sure 
> they stay in registers where needed in the first place.
> 
> 
> Try taking a performance critical loop entirely in registers, 
> and change 
> it to save to and load from memory into a register on every iteration.
> See how much slower it gets.
> 
> --Dan
> 

You, Sir, are Absolutely Right.

(and we all know there's no absolutes, so he must be relatively
absolutely right).

This reminds me about programming a C64 in assembler. Having
only three 8-bit registers, with only one of them capable of
arithmetic operations, and the other two have their own weird
addressing schemes, makes me wonder about all those great
video games and animations.

LDA ($FE,X)

vs.

LDA ($FE),Y

anyone? :-)

PLUS, you'd have to take care about the clock delays from
crossing a page boundary, beware pushing or pulling too much
from the single-page stack, and all those "bad" cycles, and...

Heh, it was all an adventure.

-gus