[pypy-svn] pypy arm-backed-float: Implement FLOAT_TRUEDIV operation

[bivab]

Author: David Schneider <david.schneider at picle.org>
Branch: arm-backed-float
Changeset: r41540:9c673870557c
Date: 2011-01-17 17:54 +0100
http://bitbucket.org/pypy/pypy/changeset/9c673870557c/

Log:	Implement FLOAT_TRUEDIV operation

diff --git a/pypy/jit/backend/arm/instructions.py b/pypy/jit/backend/arm/instructions.py
--- a/pypy/jit/backend/arm/instructions.py
+++ b/pypy/jit/backend/arm/instructions.py
@@ -132,4 +132,5 @@
     'VADD' : {'opc1':0x3, 'opc3':0},
     'VSUB' : {'opc1':0x3, 'opc3':1},
     'VMUL' : {'opc1':0x2, 'opc3':0},
+    'VDIV' : {'opc1':0x8, 'opc3':0},
 }

diff --git a/pypy/jit/backend/arm/opassembler.py b/pypy/jit/backend/arm/opassembler.py
--- a/pypy/jit/backend/arm/opassembler.py
+++ b/pypy/jit/backend/arm/opassembler.py
@@ -777,6 +777,7 @@
     emit_op_float_add = gen_emit_float_op('VADD')
     emit_op_float_sub = gen_emit_float_op('VSUB')
     emit_op_float_mul = gen_emit_float_op('VMUL')
+    emit_op_float_truediv = gen_emit_float_op('VDIV')
 
 class ResOpAssembler(GuardOpAssembler, IntOpAsslember,
                     OpAssembler, UnaryIntOpAssembler,

diff --git a/pypy/jit/backend/arm/regalloc.py b/pypy/jit/backend/arm/regalloc.py
--- a/pypy/jit/backend/arm/regalloc.py
+++ b/pypy/jit/backend/arm/regalloc.py
@@ -785,6 +785,7 @@
     prepare_op_float_add = prepare_float_op()
     prepare_op_float_sub = prepare_float_op()
     prepare_op_float_mul = prepare_float_op()
+    prepare_op_float_truediv = prepare_float_op()
 
 def make_operation_list():
     def notimplemented(self, op, fcond):