[pypy-svn] pypy arm-backed-float: Implement FLOAT_MUL operation

[bivab]

Author: David Schneider <david.schneider at picle.org>
Branch: arm-backed-float
Changeset: r41539:2a270aeaa3dc
Date: 2011-01-17 17:46 +0100
http://bitbucket.org/pypy/pypy/changeset/2a270aeaa3dc/

Log:	Implement FLOAT_MUL operation

diff --git a/pypy/jit/backend/arm/instructions.py b/pypy/jit/backend/arm/instructions.py
--- a/pypy/jit/backend/arm/instructions.py
+++ b/pypy/jit/backend/arm/instructions.py
@@ -129,6 +129,7 @@
 # based on encoding from A7.5	VFP data-processing instructions
 # opc2 is one of the parameters and therefore ignored here
 float64_data_proc_instructions = {
-    'VADD': {'opc1':0x3, 'opc3':0},
-    'VSUB': {'opc1':0x3, 'opc3':1},
+    'VADD' : {'opc1':0x3, 'opc3':0},
+    'VSUB' : {'opc1':0x3, 'opc3':1},
+    'VMUL' : {'opc1':0x2, 'opc3':0},
 }

diff --git a/pypy/jit/backend/arm/opassembler.py b/pypy/jit/backend/arm/opassembler.py
--- a/pypy/jit/backend/arm/opassembler.py
+++ b/pypy/jit/backend/arm/opassembler.py
@@ -8,7 +8,9 @@
 
 from pypy.jit.backend.arm.helper.assembler import (gen_emit_op_by_helper_call,
                                                     gen_emit_op_unary_cmp,
-                                                    gen_emit_op_ri, gen_emit_cmp_op)
+                                                    gen_emit_op_ri,
+                                                    gen_emit_cmp_op,
+                                                    gen_emit_float_op)
 from pypy.jit.backend.arm.codebuilder import ARMv7Builder, OverwritingBuilder
 from pypy.jit.backend.arm.jump import remap_frame_layout
 from pypy.jit.backend.arm.regalloc import Regalloc
@@ -772,13 +774,9 @@
 class FloatOpAssemlber(object):
     _mixin_ = True
 
-    def emit_op_float_add(self, op, arglocs, regalloc, fcon):
-        arg1, arg2, result = arglocs
-        self.mc.VADD(result.value, arg1.value, arg2.value)
-
-    def emit_op_float_sub(self, op, arglocs, regalloc, fcon):
-        arg1, arg2, result = arglocs
-        self.mc.VSUB(result.value, arg1.value, arg2.value)
+    emit_op_float_add = gen_emit_float_op('VADD')
+    emit_op_float_sub = gen_emit_float_op('VSUB')
+    emit_op_float_mul = gen_emit_float_op('VMUL')
 
 class ResOpAssembler(GuardOpAssembler, IntOpAsslember,
                     OpAssembler, UnaryIntOpAssembler,

diff --git a/pypy/jit/backend/arm/helper/assembler.py b/pypy/jit/backend/arm/helper/assembler.py
--- a/pypy/jit/backend/arm/helper/assembler.py
+++ b/pypy/jit/backend/arm/helper/assembler.py
@@ -49,3 +49,10 @@
         self.mc.MOV_ri(res.value, 0, cond=inv)
         return fcond
     return f
+
+def gen_emit_float_op(opname):
+    op_rr = getattr(AbstractARMv7Builder, opname)
+    def f(self, op, arglocs, regalloc, fcon):
+        arg1, arg2, result = arglocs
+        op_rr(self.mc, result.value, arg1.value, arg2.value)
+    return f

diff --git a/pypy/jit/backend/arm/regalloc.py b/pypy/jit/backend/arm/regalloc.py
--- a/pypy/jit/backend/arm/regalloc.py
+++ b/pypy/jit/backend/arm/regalloc.py
@@ -784,6 +784,7 @@
 
     prepare_op_float_add = prepare_float_op()
     prepare_op_float_sub = prepare_float_op()
+    prepare_op_float_mul = prepare_float_op()
 
 def make_operation_list():
     def notimplemented(self, op, fcond):