[ANNOUNCE] MyHDL 0.5 released

[Michael]

Jan Decaluwe wrote:

> I'm pleased to announce the release of MyHDL 0.5.
> 
> MyHDL is an open-source package for using Python as a hardware
> description and verification language. Moreover, it can convert
> a design to Verilog. Thus, MyHDL provides a complete path
> from Python to silicon.

Jan,


I'm not sure if you read c.l.p, but if you do...

I'm looking at the website and I see that you've now got an example showing
translation to verilog - which is really cool. I also saw that someone's
done what I view as a complex example - specifically the MU0 example [*]
(which is a tutorial I remember from student days!) as a MyHDL simulation.

   * http://article.gmane.org/gmane.comp.python.myhdl/19/match=mu0

One question I've got, mainly because it strikes me as very intriguing is
do you know if the MU0 processor as described is synthesisable or have a
feeling as to how much work would be needed for it to be synthesisable?

I've been watching your project grow over the past couple of years with
great interest though little actual need at the moment, but for me seeing
MU0 crop up piques my interest because that shows that MyHDL is getting up
to a very interesting level.

This probably comes across as a bit random, but it struck me as quite
exciting to see :-)

Regards,


Michael.