[Python-checkins] CVS: python/dist/src/Modules fpectlmodule.c,2.11,2.12

[Guido van Rossum]

Update of /cvsroot/python/python/dist/src/Modules
In directory slayer.i.sourceforge.net:/tmp/cvs-serv21744

Modified Files:
	fpectlmodule.c 
Log Message:
Use PyOS_setsig() instead of signal().  Also remove redundant spaces
from the FreeBSD code.


Index: fpectlmodule.c
===================================================================
RCS file: /cvsroot/python/python/dist/src/Modules/fpectlmodule.c,v
retrieving revision 2.11
retrieving revision 2.12
diff -C2 -r2.11 -r2.12
*** fpectlmodule.c	2000/09/19 13:35:40	2.11
--- fpectlmodule.c	2000/09/21 14:32:04	2.12
***************
*** 131,135 ****
  		 _ABORT_ON_ERROR,
  		 NULL);
!     signal(SIGFPE, handler);
  
  /*-- SunOS and Solaris ----------------------------------------------------*/
--- 131,135 ----
  		 _ABORT_ON_ERROR,
  		 NULL);
!     PyOS_setsig(SIGFPE, handler);
  
  /*-- SunOS and Solaris ----------------------------------------------------*/
***************
*** 145,149 ****
      (void) ieee_flags("clearall",mode,in,&out);
      (void) ieee_handler("set","common",(sigfpe_handler_type)handler);
!     signal(SIGFPE, handler);
  
  /*-- HPUX -----------------------------------------------------------------*/
--- 145,149 ----
      (void) ieee_flags("clearall",mode,in,&out);
      (void) ieee_handler("set","common",(sigfpe_handler_type)handler);
!     PyOS_setsig(SIGFPE, handler);
  
  /*-- HPUX -----------------------------------------------------------------*/
***************
*** 154,158 ****
  #include <math.h>
      fpsetdefaults();
!     signal(SIGFPE, handler);
  
  /*-- IBM AIX --------------------------------------------------------------*/
--- 154,158 ----
  #include <math.h>
      fpsetdefaults();
!     PyOS_setsig(SIGFPE, handler);
  
  /*-- IBM AIX --------------------------------------------------------------*/
***************
*** 162,166 ****
      fp_trap(FP_TRAP_SYNC);
      fp_enable(TRP_INVALID | TRP_DIV_BY_ZERO | TRP_OVERFLOW);
!     signal(SIGFPE, handler);
  
  /*-- DEC ALPHA OSF --------------------------------------------------------*/
--- 162,166 ----
      fp_trap(FP_TRAP_SYNC);
      fp_enable(TRP_INVALID | TRP_DIV_BY_ZERO | TRP_OVERFLOW);
!     PyOS_setsig(SIGFPE, handler);
  
  /*-- DEC ALPHA OSF --------------------------------------------------------*/
***************
*** 173,177 ****
      IEEE_TRAP_ENABLE_INV | IEEE_TRAP_ENABLE_DZE | IEEE_TRAP_ENABLE_OVF;
      ieee_set_fp_control(fp_control);
!     signal(SIGFPE, handler);
  
  /*-- Cray Unicos ----------------------------------------------------------*/
--- 173,177 ----
      IEEE_TRAP_ENABLE_INV | IEEE_TRAP_ENABLE_DZE | IEEE_TRAP_ENABLE_OVF;
      ieee_set_fp_control(fp_control);
!     PyOS_setsig(SIGFPE, handler);
  
  /*-- Cray Unicos ----------------------------------------------------------*/
***************
*** 181,191 ****
      libmset(-1);
  #endif
!     signal(SIGFPE, handler);
  
  /*-- FreeBSD ----------------------------------------------------------------*/
  #elif defined(__FreeBSD__)
!     fpresetsticky( fpgetsticky() );
!     fpsetmask( FP_X_INV | FP_X_DZ | FP_X_OFL );
!     signal( SIGFPE, handler );
  
  /*-- Linux ----------------------------------------------------------------*/
--- 181,191 ----
      libmset(-1);
  #endif
!     PyOS_setsig(SIGFPE, handler);
  
  /*-- FreeBSD ----------------------------------------------------------------*/
  #elif defined(__FreeBSD__)
!     fpresetsticky(fpgetsticky());
!     fpsetmask(FP_X_INV | FP_X_DZ | FP_X_OFL);
!     PyOS_setsig(SIGFPE, handler);
  
  /*-- Linux ----------------------------------------------------------------*/
***************
*** 197,201 ****
  #endif
      __setfpucw(0x1372);
!     signal(SIGFPE, handler);
  
  /*-- NeXT -----------------------------------------------------------------*/
--- 197,201 ----
  #endif
      __setfpucw(0x1372);
!     PyOS_setsig(SIGFPE, handler);
  
  /*-- NeXT -----------------------------------------------------------------*/
***************
*** 203,207 ****
      /* NeXT needs explicit csr set to generate SIGFPE */
      asm("fmovel     #0x1400,fpcr");   /* set OVFL and ZD bits */
!     signal(SIGFPE, handler);
  
  /*-- Microsoft Windows, NT ------------------------------------------------*/
--- 203,207 ----
      /* NeXT needs explicit csr set to generate SIGFPE */
      asm("fmovel     #0x1400,fpcr");   /* set OVFL and ZD bits */
!     PyOS_setsig(SIGFPE, handler);
  
  /*-- Microsoft Windows, NT ------------------------------------------------*/
***************
*** 212,216 ****
      unsigned int cw = _EM_INVALID | _EM_ZERODIVIDE | _EM_OVERFLOW;
      (void)_controlfp(0, cw);
!     signal(SIGFPE, handler);
  
  /*-- Give Up --------------------------------------------------------------*/
--- 212,216 ----
      unsigned int cw = _EM_INVALID | _EM_ZERODIVIDE | _EM_OVERFLOW;
      (void)_controlfp(0, cw);
!     PyOS_setsig(SIGFPE, handler);
  
  /*-- Give Up --------------------------------------------------------------*/
***************
*** 224,233 ****
  {
  #ifdef __FreeBSD__
!     fpresetsticky( fpgetsticky() );
!     fpsetmask( 0 );
  #else
      fputs("Operation not implemented\n", stderr);
  #endif
!     Py_INCREF (Py_None);
      return Py_None;
  }
--- 224,233 ----
  {
  #ifdef __FreeBSD__
!     fpresetsticky(fpgetsticky());
!     fpsetmask(0);
  #else
      fputs("Operation not implemented\n", stderr);
  #endif
!     Py_INCREF(Py_None);
      return Py_None;
  }