[issue31119] Signal tripped flags need memory barriers

[Armin Rigo]

Armin Rigo added the comment:

For reference, no, it can't happen on x86 or x86-64.  I've found that this simplified model actually works for reasoning about ordering at the hardware level: think about each core as a cache-less machine that always *reads* from the central RAM, but that has a delay for writes---i.e. writes issued by a core are queued internally, and actually sent to the central RAM at some unspecified later time, but in order.

(Of course that model fails on other machines like ARM.)

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nosy: +arigo

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<http://bugs.python.org/issue31119>
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