[pypy-commit] pypy arm64: in progress

[fijal]

Author: Maciej Fijalkowski <fijall at gmail.com>
Branch: arm64
Changeset: r96220:d301852919b9
Date: 2019-03-06 15:04 +0000
http://bitbucket.org/pypy/pypy/changeset/d301852919b9/

Log:	in progress

diff --git a/rpython/jit/backend/aarch64/codebuilder.py b/rpython/jit/backend/aarch64/codebuilder.py
--- a/rpython/jit/backend/aarch64/codebuilder.py
+++ b/rpython/jit/backend/aarch64/codebuilder.py
@@ -114,6 +114,11 @@
         base = 0b11101011000
         self.write32((base << 21) | (rm << 16) | (rn << 5) | 0b11111)
 
+    def CMP_ri(self, rn, imm):
+        base = 0b1111000100
+        assert 0 <= imm <= 4095
+        self.write32((base << 22) | (imm << 10) | (rn << 5) | 0b11111)
+
     def B_ofs(self, ofs):
         base = 0b000101
         assert ofs & 0x3 == 0
diff --git a/rpython/jit/backend/aarch64/opassembler.py b/rpython/jit/backend/aarch64/opassembler.py
--- a/rpython/jit/backend/aarch64/opassembler.py
+++ b/rpython/jit/backend/aarch64/opassembler.py
@@ -110,6 +110,20 @@
     def emit_guard_op_guard_true(self, guard_op, fcond, arglocs):
         self._emit_guard(guard_op, fcond, arglocs)
 
+    def emit_guard_op_guard_false(self, guard_op, fcond, arglocs):
+        self._emit_guard(guard_op, c.get_opposite_of(fcond), arglocs)
+
+    def load_condition_into_cc(self, loc):
+        if not loc.is_core_reg():
+            assert loc.is_stack()
+            self.regalloc_mov(loc, r.ip0)
+            loc = r.ip0
+        self.mc.CMP_ri(loc.value, 0)
+
+    def emit_op_guard_false(self, op, arglocs):
+        self.load_condition_into_cc(arglocs[1])
+        self._emit_guard(op, c.NE, arglocs)
+
     def emit_op_label(self, op, arglocs):
         pass
 
diff --git a/rpython/jit/backend/aarch64/regalloc.py b/rpython/jit/backend/aarch64/regalloc.py
--- a/rpython/jit/backend/aarch64/regalloc.py
+++ b/rpython/jit/backend/aarch64/regalloc.py
@@ -392,17 +392,25 @@
             locs = []
         return locs
 
-    def prepare_guard_op_guard_true(self, op, prevop):
+    def guard_impl(self, op, prevop):
         fcond = self.assembler.dispatch_comparison(prevop)
         # result is in CC
+        return self._guard_impl(op), fcond
 
+    def _guard_impl(self, op):
         arglocs = [None] * (len(op.getfailargs()) + 1)
         arglocs[0] = imm(self.frame_manager.get_frame_depth())
         failargs = op.getfailargs()
         for i in range(len(failargs)):
             if failargs[i]:
                 arglocs[i + 1] = self.loc(failargs[i])
-        return arglocs, fcond
+        return arglocs
+
+    prepare_guard_op_guard_true = guard_impl
+    prepare_guard_op_guard_false = guard_impl
+
+    prepare_op_guard_true = _guard_impl
+    prepare_op_guard_false = _guard_impl
 
     prepare_op_nursery_ptr_increment = prepare_op_int_add