[pypy-commit] pypy arm64: int_sub

[fijal]

Author: Maciej Fijalkowski <fijall at gmail.com>
Branch: arm64
Changeset: r96218:88c9f1531c0d
Date: 2019-03-06 14:35 +0000
http://bitbucket.org/pypy/pypy/changeset/88c9f1531c0d/

Log:	int_sub

diff --git a/rpython/jit/backend/aarch64/opassembler.py b/rpython/jit/backend/aarch64/opassembler.py
--- a/rpython/jit/backend/aarch64/opassembler.py
+++ b/rpython/jit/backend/aarch64/opassembler.py
@@ -13,6 +13,29 @@
     def emit_op_int_add(self, op, arglocs):
         return self.int_add_impl(op, arglocs)
 
+    def int_sub_impl(self, op, arglocs, flags=0):
+        l0, l1, res = arglocs
+        if flags:
+            xxx
+            s = 1
+        else:
+            s = 0
+        if l0.is_imm():
+            value = l0.getint()
+            assert value >= 0
+            # reverse substract ftw
+            XX
+            self.mc.RSB_ri(res.value, l1.value, value)
+        elif l1.is_imm():
+            value = l1.getint()
+            assert value >= 0
+            self.mc.SUB_ri(res.value, l0.value, value)
+        else:
+            self.mc.SUB_rr(res.value, l0.value, l1.value)
+
+    def emit_op_int_sub(self, op, arglocs):
+        self.int_sub_impl(op, arglocs)
+
     emit_op_nursery_ptr_increment = emit_op_int_add
 
     def int_add_impl(self, op, arglocs, ovfcheck=False):
diff --git a/rpython/jit/backend/aarch64/regalloc.py b/rpython/jit/backend/aarch64/regalloc.py
--- a/rpython/jit/backend/aarch64/regalloc.py
+++ b/rpython/jit/backend/aarch64/regalloc.py
@@ -298,7 +298,6 @@
     def prepare_op_int_add(self, op):
         boxes = op.getarglist()
         a0, a1 = boxes
-        # XXX support immediates
         imm_a0 = check_imm_box(a0)
         imm_a1 = check_imm_box(a1)
         if not imm_a0 and imm_a1:
@@ -314,6 +313,8 @@
         res = self.force_allocate_reg(op)
         return [l0, l1, res]
 
+    prepare_op_int_sub = prepare_op_int_add
+
     def prepare_int_cmp(self, op, res_in_cc):
         boxes = op.getarglist()
         arg0, arg1 = boxes