[pypy-commit] pypy arm64: hopefully finish translation

[fijal]

Author: Maciej Fijalkowski <fijall at gmail.com>
Branch: arm64
Changeset: r96874:3a7beb528024
Date: 2019-06-27 16:58 +0000
http://bitbucket.org/pypy/pypy/changeset/3a7beb528024/

Log:	hopefully finish translation

diff --git a/rpython/jit/backend/aarch64/assembler.py b/rpython/jit/backend/aarch64/assembler.py
--- a/rpython/jit/backend/aarch64/assembler.py
+++ b/rpython/jit/backend/aarch64/assembler.py
@@ -692,8 +692,8 @@
         size = self.mc.get_relative_pos() 
         res = self.mc.materialize(self.cpu, allblocks,
                                    self.cpu.gc_ll_descr.gcrootmap)
-        self.cpu.codemap.register_codemap(
-            self.codemap.get_final_bytecode(res, size))
+        #self.cpu.codemap.register_codemap(
+        #    self.codemap.get_final_bytecode(res, size))
         return res
 
     def patch_trace(self, faildescr, looptoken, bridge_addr, regalloc):
@@ -1039,12 +1039,7 @@
         #    mc.STR_rr(source.value, base.value, r.ip1)
 
     def load_reg(self, mc, target, base, ofs=0, helper=r.ip0):
-        if target.is_vfp_reg():
-            return self._load_vfp_reg(mc, target, base, ofs)
-        elif target.is_core_reg():
-            return self._load_core_reg(mc, target, base, ofs, helper)
-
-    def _load_core_reg(self, mc, target, base, ofs, helper):
+        assert target.is_core_reg()
         if check_imm_arg(abs(ofs)):
             mc.LDR_ri(target.value, base.value, ofs)
         else:
@@ -1101,7 +1096,7 @@
     print "[ARM64/asm] %s not implemented" % op.getopname()
     raise NotImplementedError(op)
 
-def notimplemented_guard_op(self, op, fcond, arglocs):
+def notimplemented_guard_op(self, op, guard_op, fcond, arglocs):
     print "[ARM64/asm] %s not implemented" % op.getopname()
     raise NotImplementedError(op)
 
diff --git a/rpython/jit/backend/aarch64/callbuilder.py b/rpython/jit/backend/aarch64/callbuilder.py
--- a/rpython/jit/backend/aarch64/callbuilder.py
+++ b/rpython/jit/backend/aarch64/callbuilder.py
@@ -97,9 +97,11 @@
     def load_result(self):
         resloc = self.resloc
         if self.restype == 'S':
+            assert False, "not supported yet"
             XXX
             self.mc.VMOV_sc(resloc.value, r.s0.value)
         elif self.restype == 'L':
+            assert False, "not possible on 64bit backend"
             YYY
             assert resloc.is_vfp_reg()
             self.mc.FMDRR(resloc.value, r.r0.value, r.r1.value)
@@ -139,10 +141,9 @@
         # Save this thread's shadowstack pointer into r7, for later comparison
         gcrootmap = self.asm.cpu.gc_ll_descr.gcrootmap
         if gcrootmap:
-            XXX
             rst = gcrootmap.get_root_stack_top_addr()
-            self.mc.gen_load_int(r.r5.value, rst)
-            self.mc.LDR_ri(r.r7.value, r.r5.value)
+            self.mc.gen_load_int(r.x19.value, rst)
+            self.mc.LDR_ri(r.x20.value, r.x19.value)
 
         # change 'rpy_fastgil' to 0 (it should be non-zero right now)
         self.mc.DMB()
@@ -198,15 +199,14 @@
 
     def move_real_result_and_call_reacqgil_addr(self, fastgil):
         # try to reacquire the lock.
-        #     XXX r5 == &root_stack_top
-        #     r6 == fastgil
-        #     XXX r7 == previous value of root_stack_top
+        #     x19 == &root_stack_top
+        #     x20 == previous value of root_stack_top
         self.mc.gen_load_int(r.ip1.value, fastgil)
         self.mc.LDAXR(r.x1.value, r.ip1.value)    # load the lock value
         self.mc.MOVZ_r_u16(r.ip0.value, 1, 0)
         self.mc.CMP_ri(r.x1.value, 0)            # is the lock free?
         if self.asm.cpu.gc_ll_descr.gcrootmap:
-            jump_val = XXX
+            jump_val = 0 # XXX
         else:
             jump_val = 3 * 4
         self.mc.B_ofs_cond(jump_val, c.NE)
@@ -220,15 +220,16 @@
         # 'EQ is true', or equivalently by 'r3 == 0'.
         #
         if self.asm.cpu.gc_ll_descr.gcrootmap:
-            XXX
+            raise Exception("not implemented yet")
             # When doing a call_release_gil with shadowstack, there
             # is the risk that the 'rpy_fastgil' was free but the
             # current shadowstack can be the one of a different
             # thread.  So here we check if the shadowstack pointer
             # is still the same as before we released the GIL (saved
-            # in 'r7'), and if not, we fall back to 'reacqgil_addr'.
-            self.mc.LDR_ri(r.ip.value, r.r5.value, cond=c.EQ)
-            self.mc.CMP_rr(r.ip.value, r.r7.value, cond=c.EQ)
+            # in 'x20'), and if not, we fall back to 'reacqgil_addr'.
+            self.mc.LDR_ri(r.ip0.value, r.x19.value)
+            self.mc.CMP_rr(r.ip0.value, r.x20.value)
+            XXX
             b1_location = self.mc.currpos()
             self.mc.BKPT()                       # BEQ below
             # there are two cases here: either EQ was false from
diff --git a/rpython/jit/backend/aarch64/regalloc.py b/rpython/jit/backend/aarch64/regalloc.py
--- a/rpython/jit/backend/aarch64/regalloc.py
+++ b/rpython/jit/backend/aarch64/regalloc.py
@@ -814,7 +814,7 @@
         l1 = self.loc(op.getarg(1))
         imm_a1 = check_imm_box(op.getarg(1))
         if not imm_a1:
-            l1 = self.make_sure_var_in_reg(op.getarg(1), [arg])
+            l1 = self.make_sure_var_in_reg(op.getarg(1), [op.getarg(0)])
         arglocs = self._guard_impl(op)
         return [arg, l1] + arglocs
 
@@ -894,7 +894,7 @@
         arg0 = self.make_sure_var_in_reg(args[0], args)
         arg1 = self.make_sure_var_in_reg(args[1], args)
         res = self.force_allocate_reg(op)
-        return [arg0, arg1, args[2], args[3], res]
+        return [arg0, arg1, imm(args[2].getint()), imm(args[3].getint()), res]
 
     def prepare_op_check_memory_error(self, op):
         argloc = self.make_sure_var_in_reg(op.getarg(0))