[pypy-commit] pypy arm64: more float ops

[fijal]

Author: Maciej Fijalkowski <fijall at gmail.com>
Branch: arm64
Changeset: r96821:aba1d6e3b06a
Date: 2019-06-18 14:02 +0000
http://bitbucket.org/pypy/pypy/changeset/aba1d6e3b06a/

Log:	more float ops

diff --git a/rpython/jit/backend/aarch64/codebuilder.py b/rpython/jit/backend/aarch64/codebuilder.py
--- a/rpython/jit/backend/aarch64/codebuilder.py
+++ b/rpython/jit/backend/aarch64/codebuilder.py
@@ -187,6 +187,18 @@
         base = 0b00011110011
         self.write32((base << 21) | (rm << 16) | (0b000110 << 10) | (rn << 5) | rd)
 
+    def FCMP_dd(self, rn, rm):
+        base = 0b00011110011
+        self.write32((base << 21) | (rm << 16) | (0b001000 << 10) | (rn << 5))
+
+    def FNEG_d(self, rd, rn):
+        base = 0b0001111001100001010000
+        self.write32((base << 10) | (rn << 5) | rd)
+
+    def FABS_d(self, rd, rn):
+        base = 0b0001111001100000110000
+        self.write32((base << 10) | (rn << 5) | rd)
+
     def SUB_rr(self, rd, rn, rm, s=0):
         base = 0b11001011001 | (s << 8)
         self.write32((base << 21) | (rm << 16) | (0b11 << 13) | (rn << 5) | (rd))
diff --git a/rpython/jit/backend/aarch64/opassembler.py b/rpython/jit/backend/aarch64/opassembler.py
--- a/rpython/jit/backend/aarch64/opassembler.py
+++ b/rpython/jit/backend/aarch64/opassembler.py
@@ -24,6 +24,14 @@
     emit_op.__name__ = name
     return emit_op
 
+def gen_float_comp_op(name, flag):
+    def emit_op(self, op, arglocs):
+        l0, l1, res = arglocs
+        self.emit_float_comp_op(op, l0, l1)
+        self.mc.CSET_r_flag(res.value, c.get_opposite_of(flag))
+    emit_op.__name__ = name
+    return emit_op        
+
 class ResOpAssembler(BaseAssembler):
     def int_sub_impl(self, op, arglocs, flags=0):
         l0, l1, res = arglocs
@@ -107,6 +115,9 @@
         else:
             self.mc.CMP_rr(l0.value, l1.value)
 
+    def emit_float_comp_op(self, op, l0, l1):
+        self.mc.FCMP_dd(l0.value, l1.value)
+
     def emit_comp_op_int_lt(self, op, arglocs):
         self.emit_int_comp_op(op, arglocs[0], arglocs[1])
         return c.LT
@@ -227,6 +238,21 @@
         arg1, arg2, res = arglocs
         self.mc.FDIV_dd(res.value, arg1.value, arg2.value)    
 
+    emit_op_float_lt = gen_float_comp_op('float_lt', c.VFP_LT)
+    emit_op_float_le = gen_float_comp_op('float_le', c.VFP_LE)
+    emit_op_float_eq = gen_float_comp_op('float_eq', c.EQ)
+    emit_op_float_ne = gen_float_comp_op('float_ne', c.NE)
+    emit_op_float_gt = gen_float_comp_op('float_gt', c.GT)
+    emit_op_float_ge = gen_float_comp_op('float_ge', c.GE)
+
+    def emit_op_float_neg(self, op, arglocs):
+        arg, res = arglocs
+        self.mc.FNEG_d(res.value, arg.value)
+
+    def emit_op_float_abs(self, op, arglocs):
+        arg, res = arglocs
+        self.mc.FABS_d(res.value, arg.value)        
+
     def emit_op_load_from_gc_table(self, op, arglocs):
         res_loc, = arglocs
         index = op.getarg(0).getint()
diff --git a/rpython/jit/backend/aarch64/regalloc.py b/rpython/jit/backend/aarch64/regalloc.py
--- a/rpython/jit/backend/aarch64/regalloc.py
+++ b/rpython/jit/backend/aarch64/regalloc.py
@@ -455,6 +455,16 @@
     prepare_op_float_mul = prepare_two_regs_op
     prepare_op_float_truediv = prepare_two_regs_op
 
+    prepare_op_float_lt = prepare_two_regs_op
+    prepare_op_float_le = prepare_two_regs_op
+    prepare_op_float_eq = prepare_two_regs_op
+    prepare_op_float_ne = prepare_two_regs_op
+    prepare_op_float_gt = prepare_two_regs_op
+    prepare_op_float_ge = prepare_two_regs_op
+
+    prepare_op_float_neg = prepare_unary
+    prepare_op_float_abs = prepare_unary
+
     # --------------------------------- fields --------------------------
 
     def prepare_op_gc_store(self, op):