[pypy-commit] pypy arm64: fix

[fijal]

Author: fijal
Branch: arm64
Changeset: r96938:3a6979dda07b
Date: 2019-07-03 16:32 +0200
http://bitbucket.org/pypy/pypy/changeset/3a6979dda07b/

Log:	fix

diff --git a/rpython/jit/backend/aarch64/opassembler.py b/rpython/jit/backend/aarch64/opassembler.py
--- a/rpython/jit/backend/aarch64/opassembler.py
+++ b/rpython/jit/backend/aarch64/opassembler.py
@@ -593,7 +593,7 @@
         # Note that the typeid half-word is at offset 0 on a little-endian
         # machine; it would be at offset 2 or 4 on a big-endian machine.
         assert self.cpu.supports_guard_gc_type
-        self.mc.LDRH_ri(r.ip0.value, loc_ptr.value)
+        self.mc.LDRH_ri(r.ip0.value, loc_ptr.value, 0)
         self.mc.gen_load_int(r.ip1.value, expected_typeid)
         self.mc.CMP_rr(r.ip0.value, r.ip1.value)