[pypy-commit] pypy arm64: add some casts

[fijal]

Author: fijal
Branch: arm64
Changeset: r96902:b96f44a61156
Date: 2019-07-01 17:29 +0200
http://bitbucket.org/pypy/pypy/changeset/b96f44a61156/

Log:	add some casts

diff --git a/rpython/jit/backend/aarch64/assembler.py b/rpython/jit/backend/aarch64/assembler.py
--- a/rpython/jit/backend/aarch64/assembler.py
+++ b/rpython/jit/backend/aarch64/assembler.py
@@ -676,7 +676,7 @@
         # r0.
 
         self.mc.B_ofs_cond(10 * 4, c.LO) # 4 for gcmap load, 5 for BL, 1 for B_ofs_cond
-        self.mc.gen_load_int_full(r.ip1.value, gcmap)
+        self.mc.gen_load_int_full(r.ip1.value, rffi.cast(lltype.Signed, gcmap))
 
         self.mc.BL(self.malloc_slowpath)
 
@@ -699,7 +699,7 @@
         self.mc.CMP_rr(r.x1.value, r.ip0.value)
         #
         self.mc.B_ofs_cond(40, c.LO) # see calculations in malloc_cond
-        self.mc.gen_load_int_full(r.ip1.value, gcmap)
+        self.mc.gen_load_int_full(r.ip1.value, rffi.cast(lltype.Signed, gcmap))
 
         self.mc.BL(self.malloc_slowpath)
 
@@ -770,7 +770,7 @@
         pmc.B_ofs_cond(currpos - jmp_adr0, c.GT)
         #
         # save the gcmap
-        self.mc.gen_load_int_full(r.ip1.value, gcmap)
+        self.mc.gen_load_int_full(r.ip1.value, rffi.cast(lltype.Signed, gcmap))
         #
 
         if kind == rewrite.FLAG_ARRAY: