[pypy-commit] pypy arm64: (fijal, arigo) ovf ops
fijal
pypy.commits at gmail.com
Wed Apr 17 06:10:29 EDT 2019
Author: fijal
Branch: arm64
Changeset: r96512:a6eddad931b2
Date: 2019-04-17 12:09 +0200
http://bitbucket.org/pypy/pypy/changeset/a6eddad931b2/
Log: (fijal, arigo) ovf ops
diff --git a/rpython/jit/backend/aarch64/codebuilder.py b/rpython/jit/backend/aarch64/codebuilder.py
--- a/rpython/jit/backend/aarch64/codebuilder.py
+++ b/rpython/jit/backend/aarch64/codebuilder.py
@@ -163,6 +163,11 @@
base = 0b11101011000
self.write32((base << 21) | (rm << 16) | (rn << 5) | 0b11111)
+ def CMP_rr_shifted(self, rn, rm, imm):
+ base = 0b11101011100
+ assert 0 <= imm <= 63
+ self.write32((base << 21) | (rm << 16) | (imm << 10) | (rn << 5) | 0b11111)
+
def CMP_ri(self, rn, imm):
base = 0b1111000100
assert 0 <= imm <= 4095
diff --git a/rpython/jit/backend/aarch64/opassembler.py b/rpython/jit/backend/aarch64/opassembler.py
--- a/rpython/jit/backend/aarch64/opassembler.py
+++ b/rpython/jit/backend/aarch64/opassembler.py
@@ -62,10 +62,9 @@
def emit_comp_op_int_mul_ovf(self, op, arglocs):
reg1, reg2, res = arglocs
+ self.mc.SMULH_rr(r.ip0.value, reg1.value, reg2.value)
self.mc.MUL_rr(res.value, reg1.value, reg2.value)
- xxx # what to do here?
- self.mc.SMULH_rr(res.value, reg1.value, reg2.value)
- self.mc.CMP_ri(r.ip0.value, 0)
+ self.mc.CMP_rr_shifted(r.ip0.value, res.value, 63)
def emit_op_int_and(self, op, arglocs):
l0, l1, res = arglocs
diff --git a/rpython/jit/backend/aarch64/regalloc.py b/rpython/jit/backend/aarch64/regalloc.py
--- a/rpython/jit/backend/aarch64/regalloc.py
+++ b/rpython/jit/backend/aarch64/regalloc.py
@@ -485,7 +485,7 @@
self.assembler.dispatch_comparison(prev_op)
# result in CC
if prev_op.opnum == rop.INT_MUL_OVF:
- return self._guard_impl(guard_op), c.GT
+ return self._guard_impl(guard_op), c.EQ
return self._guard_impl(guard_op), c.VC
prepare_guard_op_guard_no_overflow = prepare_guard_op_guard_overflow
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