[pypy-commit] pypy default: use constants to make the code less confusing
cfbolz
pypy.commits at gmail.com
Fri Sep 8 15:22:46 EDT 2017
Author: Carl Friedrich Bolz-Tereick <cfbolz at gmx.de>
Branch:
Changeset: r92361:7de7062d9526
Date: 2017-09-08 17:01 +0200
http://bitbucket.org/pypy/pypy/changeset/7de7062d9526/
Log: use constants to make the code less confusing
diff --git a/rpython/jit/backend/llsupport/regalloc.py b/rpython/jit/backend/llsupport/regalloc.py
--- a/rpython/jit/backend/llsupport/regalloc.py
+++ b/rpython/jit/backend/llsupport/regalloc.py
@@ -10,6 +10,10 @@
except ImportError:
OrderedDict = dict # too bad
+SAVE_DEFAULT_REGS = 0
+SAVE_GCREF_REGS = 2
+SAVE_ALL_REGS = 1
+
class TempVar(AbstractValue):
def __init__(self):
pass
@@ -586,7 +590,8 @@
force_store, save_all_regs)
def spill_or_move_registers_before_call(self, save_sublist,
- force_store=[], save_all_regs=0):
+ force_store=[],
+ save_all_regs=SAVE_DEFAULT_REGS):
"""Spill or move some registers before a call.
By default, this means: for every register in 'save_sublist',
@@ -602,8 +607,9 @@
valid, but only *if they are in self.save_around_call_regs,*
not if they are callee-saved registers!
- 'save_all_regs' can be 0 (default set of registers), 1 (do that
- for all registers), or 2 (default + gc ptrs).
+ 'save_all_regs' can be SAVE_DEFAULT_REGS (default set of registers),
+ SAVE_ALL_REGS (do that for all registers), or SAVE_GCREF_REGS (default
+ + gc ptrs).
Overview of what we do (the implementation does it differently,
for the same result):
@@ -651,11 +657,11 @@
new_free_regs.append(reg)
continue
- if save_all_regs == 1:
+ if save_all_regs == SAVE_ALL_REGS:
# we need to spill all registers in this mode
self._bc_spill(v, new_free_regs)
#
- elif save_all_regs == 2 and v.type == REF:
+ elif save_all_regs == SAVE_GCREF_REGS and v.type == REF:
# we need to spill all GC ptrs in this mode
self._bc_spill(v, new_free_regs)
#
diff --git a/rpython/jit/backend/x86/regalloc.py b/rpython/jit/backend/x86/regalloc.py
--- a/rpython/jit/backend/x86/regalloc.py
+++ b/rpython/jit/backend/x86/regalloc.py
@@ -2,13 +2,13 @@
""" Register allocation scheme.
"""
-import os, sys
from rpython.jit.backend.llsupport import symbolic
from rpython.jit.backend.llsupport.descr import CallDescr, unpack_arraydescr
from rpython.jit.backend.llsupport.gcmap import allocate_gcmap
from rpython.jit.backend.llsupport.regalloc import (FrameManager, BaseRegalloc,
RegisterManager, TempVar, compute_vars_longevity, is_comparison_or_ovf_op,
- valid_addressing_size, get_scale)
+ valid_addressing_size, get_scale, SAVE_DEFAULT_REGS, SAVE_GCREF_REGS,
+ SAVE_ALL_REGS)
from rpython.jit.backend.x86 import rx86
from rpython.jit.backend.x86.arch import (WORD, JITFRAME_FIXED_SIZE, IS_X86_32,
IS_X86_64, DEFAULT_FRAME_BYTES)
@@ -23,12 +23,11 @@
from rpython.jit.codewriter.effectinfo import EffectInfo
from rpython.jit.metainterp.history import (Const, ConstInt, ConstPtr,
ConstFloat, INT, REF, FLOAT, VECTOR, TargetToken, AbstractFailDescr)
-from rpython.jit.metainterp.resoperation import rop, ResOperation
+from rpython.jit.metainterp.resoperation import rop
from rpython.jit.metainterp.resume import AccumInfo
from rpython.rlib import rgc
from rpython.rlib.objectmodel import we_are_translated
from rpython.rlib.rarithmetic import r_longlong, r_uint
-from rpython.rtyper.annlowlevel import cast_instance_to_gcref
from rpython.rtyper.lltypesystem import lltype, rffi, rstr
from rpython.rtyper.lltypesystem.lloperation import llop
from rpython.jit.backend.x86.regloc import AddressLoc
@@ -799,25 +798,29 @@
# we need to save registers on the stack:
#
# - at least the non-callee-saved registers
+ # (gc_level == SAVE_DEFAULT_REGS)
#
- # - if gc_level > 0, we save also the callee-saved registers that
- # contain GC pointers
+ # - if gc_level == SAVE_GCREF_REGS we save also the callee-saved
+ # registers that contain GC pointers
#
- # - gc_level == 2 for CALL_MAY_FORCE or CALL_ASSEMBLER. We
+ # - gc_level == SAVE_ALL_REGS for CALL_MAY_FORCE or CALL_ASSEMBLER. We
# have to save all regs anyway, in case we need to do
# cpu.force(). The issue is that grab_frame_values() would
# not be able to locate values in callee-saved registers.
#
- save_all_regs = gc_level == 2
+ if gc_level == SAVE_ALL_REGS:
+ save_all_regs = SAVE_ALL_REGS
+ else:
+ save_all_regs = SAVE_DEFAULT_REGS
self.xrm.before_call(save_all_regs=save_all_regs)
- if gc_level == 1:
+ if gc_level == SAVE_GCREF_REGS:
gcrootmap = self.assembler.cpu.gc_ll_descr.gcrootmap
- # we save all the registers for shadowstack and asmgcc for now
+ # we save all the GCREF registers for shadowstack and asmgcc for now
# --- for asmgcc too: we can't say "register x is a gc ref"
# without distinguishing call sites, which we don't do any
# more for now.
if gcrootmap: # and gcrootmap.is_shadow_stack:
- save_all_regs = 2
+ save_all_regs = SAVE_GCREF_REGS
self.rm.before_call(save_all_regs=save_all_regs)
if op.type != 'v':
if op.type == FLOAT:
@@ -841,11 +844,11 @@
#
effectinfo = calldescr.get_extra_info()
if guard_not_forced:
- gc_level = 2
+ gc_level = SAVE_ALL_REGS
elif effectinfo is None or effectinfo.check_can_collect():
- gc_level = 1
+ gc_level = SAVE_GCREF_REGS
else:
- gc_level = 0
+ gc_level = SAVE_DEFAULT_REGS
#
self._call(op, [imm(size), sign_loc] +
[self.loc(op.getarg(i)) for i in range(op.numargs())],
@@ -909,7 +912,7 @@
def _consider_call_assembler(self, op):
locs = self.locs_for_call_assembler(op)
- self._call(op, locs, gc_level=2)
+ self._call(op, locs, gc_level=SAVE_ALL_REGS)
consider_call_assembler_i = _consider_call_assembler
consider_call_assembler_r = _consider_call_assembler
consider_call_assembler_f = _consider_call_assembler
More information about the pypy-commit
mailing list