[pypy-commit] pypy regalloc-playground: float coalescing support

[cfbolz]

Author: Carl Friedrich Bolz-Tereick <cfbolz at gmx.de>
Branch: regalloc-playground
Changeset: r92338:f60a7734d1b4
Date: 2017-09-06 18:37 +0200
http://bitbucket.org/pypy/pypy/changeset/f60a7734d1b4/

Log:	float coalescing support

diff --git a/rpython/jit/backend/llsupport/test/test_regalloc_integration.py b/rpython/jit/backend/llsupport/test/test_regalloc_integration.py
--- a/rpython/jit/backend/llsupport/test/test_regalloc_integration.py
+++ b/rpython/jit/backend/llsupport/test/test_regalloc_integration.py
@@ -77,17 +77,22 @@
     def fppii(x, y, i, j):
         return 19
 
+    def ff(x, y):
+        return x + y + 0.1
+
     F1PTR = lltype.Ptr(lltype.FuncType([lltype.Signed], lltype.Signed))
     F2PTR = lltype.Ptr(lltype.FuncType([lltype.Signed]*2, lltype.Signed))
     F10PTR = lltype.Ptr(lltype.FuncType([lltype.Signed]*10, lltype.Signed))
     FGCREFPTR = lltype.Ptr(lltype.FuncType([llmemory.GCREF], lltype.Signed))
     FPPIIPTR = lltype.Ptr(lltype.FuncType([llmemory.GCREF, llmemory.GCREF, lltype.Signed, lltype.Signed], lltype.Signed))
+    FFPTR = lltype.Ptr(lltype.FuncType([lltype.Float]*2, lltype.Float))
 
     f1ptr = llhelper(F1PTR, f1)
     f2ptr = llhelper(F2PTR, f2)
     f10ptr = llhelper(F10PTR, f10)
     fgcrefptr = llhelper(FGCREFPTR, fgcref)
     fppiiptr = llhelper(FPPIIPTR, fppii)
+    ffptr = llhelper(FFPTR, ff)
 
     f1_calldescr = cpu.calldescrof(F1PTR.TO, F1PTR.TO.ARGS, F1PTR.TO.RESULT,
                                    EffectInfo.MOST_GENERAL)
@@ -99,6 +104,8 @@
                                        EffectInfo.MOST_GENERAL)
     fppii_calldescr = cpu.calldescrof(FPPIIPTR.TO, FPPIIPTR.TO.ARGS, FPPIIPTR.TO.RESULT,
                                       EffectInfo.MOST_GENERAL)
+    ff_calldescr = cpu.calldescrof(FFPTR.TO, FFPTR.TO.ARGS, FFPTR.TO.RESULT,
+                                   EffectInfo.MOST_GENERAL)
 
     namespace = locals().copy()
 
diff --git a/rpython/jit/backend/x86/reghint.py b/rpython/jit/backend/x86/reghint.py
--- a/rpython/jit/backend/x86/reghint.py
+++ b/rpython/jit/backend/x86/reghint.py
@@ -76,6 +76,8 @@
         else:
             self._consider_binop_symm(op, position)
 
+    consider_nursery_ptr_increment = consider_int_add
+
     def consider_int_sub(self, op, position):
         y = op.getarg(1)
         if isinstance(y, ConstInt) and rx86.fits_in_32bits(-y.value):
@@ -83,8 +85,17 @@
         else:
             self._consider_binop(op, position)
 
+    def _consider_float_op(self, op, position):
+        x = op.getarg(0)
+        if not isinstance(x, Const):
+            self.longevity.try_use_same_register(x, op)
 
-    consider_nursery_ptr_increment = consider_int_add
+    consider_float_add = _consider_float_op
+    consider_float_sub = _consider_float_op
+    consider_float_mul = _consider_float_op
+    consider_float_truediv = _consider_float_op
+    consider_float_neg = _consider_float_op
+    consider_float_abs = _consider_float_op
 
     def consider_int_lshift(self, op, position):
         x, y = op.getarg(0), op.getarg(1)
diff --git a/rpython/jit/backend/x86/test/test_regalloc.py b/rpython/jit/backend/x86/test/test_regalloc.py
--- a/rpython/jit/backend/x86/test/test_regalloc.py
+++ b/rpython/jit/backend/x86/test/test_regalloc.py
@@ -220,6 +220,19 @@
         # that would break coalescing between i7 and i9)
         assert op.args[1][0] is add1.args[-1]
 
+    def test_coalescing_float(self):
+        ops = '''
+        [f0, f1, f3]
+        f7 = float_add(f0, f1)
+        f8 = float_add(f7, f3)
+        f9 = call_f(ConstClass(ffptr), f8, 1.0, descr=ff_calldescr)
+        i10 = float_ne(f9, 0.0)
+        guard_true(i10) []
+        finish(f9)
+        '''
+        self.interpret(ops, [5.0, 6.0, 8.0])
+        assert len(self.filter_log_moves()) == 3
+
     def test_malloc(self, monkeypatch):
         ops = '''
         [i0]