[pypy-commit] pypy default: add one test and add signextenstion needed for one case (s390x)

[plan_rich]

Author: Richard Plangger <planrichi at gmail.com>
Branch: 
Changeset: r88247:ce81e2bb2517
Date: 2016-11-09 09:40 +0100
http://bitbucket.org/pypy/pypy/changeset/ce81e2bb2517/

Log:	add one test and add signextenstion needed for one case (s390x)

diff --git a/rpython/jit/backend/zarch/instructions.py b/rpython/jit/backend/zarch/instructions.py
--- a/rpython/jit/backend/zarch/instructions.py
+++ b/rpython/jit/backend/zarch/instructions.py
@@ -76,7 +76,6 @@
     'CLGRJ':   ('rie_b',  ['\xEC','\x65']),
     # compare and swap
     'CSG':     ('rsy_a', ['\xEB','\x30']),
-
 }
 
 logic_mnemonic_codes = {
@@ -340,7 +339,7 @@
     'VLVG':  ('vrs_b', ['\xE7','\x22']),
     'VLGV':  ('vrs_c', ['\xE7','\x21']),
 
-    # '': ('', ['','']),
+    'VSEG':  ('vrr_a', ['\xE7','\x5F'], 'v,v,m'),
 }
 
 all_mnemonic_codes.update(arith_mnemonic_codes)
diff --git a/rpython/jit/backend/zarch/vector_ext.py b/rpython/jit/backend/zarch/vector_ext.py
--- a/rpython/jit/backend/zarch/vector_ext.py
+++ b/rpython/jit/backend/zarch/vector_ext.py
@@ -139,6 +139,8 @@
             self.mc.VLVG(resloc, r.SCRATCH, l.addr(0), l.itemsize_to_mask(nsize))
             self.mc.VLGV(r.SCRATCH, loc0, l.addr(1), l.itemsize_to_mask(osize))
             self.mc.VLVG(resloc, r.SCRATCH, l.addr(1), l.itemsize_to_mask(nsize))
+            if nsize == 8:
+                self.mc.VSEG(resloc, resloc, l.itemsize_to_mask(osize))
 
     def emit_vec_float_abs(self, op, arglocs, regalloc):
         resloc, argloc, sizeloc = arglocs
diff --git a/rpython/jit/metainterp/optimizeopt/schedule.py b/rpython/jit/metainterp/optimizeopt/schedule.py
--- a/rpython/jit/metainterp/optimizeopt/schedule.py
+++ b/rpython/jit/metainterp/optimizeopt/schedule.py
@@ -14,6 +14,7 @@
 from rpython.jit.metainterp.jitexc import NotAVectorizeableLoop, NotAProfitableLoop
 from rpython.rtyper.lltypesystem.lloperation import llop
 from rpython.rtyper.lltypesystem import lltype
+from rpython.rlib.debug import debug_print
 
 
 def forwarded_vecinfo(op):
@@ -315,11 +316,8 @@
 
 def failnbail_transformation(msg):
     msg = '%s\n' % msg
-    if we_are_translated():
-        llop.debug_print(lltype.Void, msg)
-    else:
-        import pdb; pdb.set_trace()
-    raise NotImplementedError(msg)
+    debug_print(msg)
+    raise NotAVectorizeableLoop
 
 def turn_into_vector(state, pack):
     """ Turn a pack into a vector instruction """
diff --git a/rpython/jit/metainterp/test/test_vector.py b/rpython/jit/metainterp/test/test_vector.py
--- a/rpython/jit/metainterp/test/test_vector.py
+++ b/rpython/jit/metainterp/test/test_vector.py
@@ -860,6 +860,37 @@
         free_raw_storage(vb)
         free_raw_storage(vc)
 
+    def test_float_int32_casts(self):
+        myjitdriver = JitDriver(greens = [], reds = 'auto', vectorize=True)
+        def f(bytecount, va, vb, vc):
+            i = 0
+            j = 0
+            while i < bytecount:
+                myjitdriver.jit_merge_point()
+                a = raw_storage_getitem(rffi.DOUBLE,va,j)
+                b = raw_storage_getitem(rffi.INT,vb,i)
+                c = a+rffi.cast(rffi.DOUBLE,b)
+                raw_storage_setitem(vc, j, c)
+                i += 4
+                j += 8
+
+        count = 32
+        va = alloc_raw_storage(8*count, zero=True)
+        vb = alloc_raw_storage(4*count, zero=True)
+        for i,v in enumerate([1.0,2.0,3.0,4.0]*(count/4)):
+            raw_storage_setitem(va, i*8, rffi.cast(rffi.DOUBLE,v))
+        for i,v in enumerate([-1,-2,-3,-4]*(count/4)):
+            raw_storage_setitem(vb, i*4, rffi.cast(rffi.INT,v))
+        vc = alloc_raw_storage(8*count, zero=True)
+        self.meta_interp(f, [8*count, va, vb, vc], vec=True)
+
+        for i in range(count):
+            assert raw_storage_getitem(rffi.DOUBLE,vc,i*8) == 0.0
+
+        free_raw_storage(va)
+        free_raw_storage(vb)
+        free_raw_storage(vc)
+
 
 class TestLLtype(LLJitMixin, VectorizeTests):
     # skip some tests on this backend