[pypy-commit] pypy default: (s390x) merged s390x-5.3-catchup
plan_rich
pypy.commits at gmail.com
Tue Jun 7 09:06:13 EDT 2016
Author: Richard Plangger <planrichi at gmail.com>
Branch:
Changeset: r84995:02f61acb357d
Date: 2016-06-07 15:04 +0200
http://bitbucket.org/pypy/pypy/changeset/02f61acb357d/
Log: (s390x) merged s390x-5.3-catchup
diff --git a/rpython/jit/backend/ppc/regalloc.py b/rpython/jit/backend/ppc/regalloc.py
--- a/rpython/jit/backend/ppc/regalloc.py
+++ b/rpython/jit/backend/ppc/regalloc.py
@@ -439,7 +439,7 @@
prepare_int_lshift = helper.prepare_binary_op
prepare_int_rshift = helper.prepare_binary_op
prepare_uint_rshift = helper.prepare_binary_op
- prepare_uint_mul_high = helper.prepare_binary_op
+ prepare_uint_mul_high = helper.prepare_int_mul_ovf
prepare_int_add_ovf = helper.prepare_binary_op
prepare_int_sub_ovf = helper.prepare_binary_op
diff --git a/rpython/jit/backend/zarch/instructions.py b/rpython/jit/backend/zarch/instructions.py
--- a/rpython/jit/backend/zarch/instructions.py
+++ b/rpython/jit/backend/zarch/instructions.py
@@ -29,6 +29,7 @@
'MGHI': ('ri', ['\xA7','\x0D']),
'MSGFI': ('ril', ['\xC2','\x00']),
'MLGR': ('rre', ['\xB9','\x86'], 'eo,r'),
+ 'MLG': ('rxy', ['\xE3','\x86'], 'eo,bid'),
# div/mod
'DSGR': ('rre', ['\xB9','\x0D'], 'eo,r'),
'DSG': ('rxy', ['\xE3','\x0D'], 'eo,bidl'),
diff --git a/rpython/jit/backend/zarch/opassembler.py b/rpython/jit/backend/zarch/opassembler.py
--- a/rpython/jit/backend/zarch/opassembler.py
+++ b/rpython/jit/backend/zarch/opassembler.py
@@ -160,11 +160,15 @@
omc.BRC(c.ANY, l.imm(label_end - jmp_neither_lqlr_overflow))
omc.overwrite()
- emit_int_floordiv = gen_emit_div_mod('DSGR', 'DSG')
- emit_uint_floordiv = gen_emit_div_mod('DLGR', 'DLG')
- # NOTE division sets one register with the modulo value, thus
- # the regalloc ensures the right register survives.
- emit_int_mod = gen_emit_div_mod('DSGR', 'DSG')
+ def emit_uint_mul_high(self, op, arglocs, regalloc):
+ r0, _, a1 = arglocs
+ # _ carries the value, contents of r0 are ignored
+ assert not r0.is_imm()
+ assert not a1.is_imm()
+ if a1.is_core_reg():
+ self.mc.MLGR(r0, a1)
+ else:
+ self.mc.MLG(r0, a1)
def emit_int_invert(self, op, arglocs, regalloc):
l0, = arglocs
diff --git a/rpython/jit/backend/zarch/regalloc.py b/rpython/jit/backend/zarch/regalloc.py
--- a/rpython/jit/backend/zarch/regalloc.py
+++ b/rpython/jit/backend/zarch/regalloc.py
@@ -733,9 +733,6 @@
prepare_int_sub_ovf = helper.prepare_int_sub
prepare_int_mul = helper.prepare_int_mul
prepare_int_mul_ovf = helper.prepare_int_mul_ovf
- prepare_int_floordiv = helper.prepare_int_div
- prepare_uint_floordiv = helper.prepare_int_div
- prepare_int_mod = helper.prepare_int_mod
prepare_nursery_ptr_increment = prepare_int_add
prepare_int_and = helper.prepare_int_logic
@@ -746,6 +743,18 @@
prepare_int_lshift = helper.prepare_int_shift
prepare_uint_rshift = helper.prepare_int_shift
+ def prepare_uint_mul_high(self, op):
+ a0 = op.getarg(0)
+ a1 = op.getarg(1)
+ if a0.is_constant():
+ a0, a1 = a1, a0
+ if helper.check_imm32(a1):
+ l1 = self.ensure_reg(a1)
+ else:
+ l1 = self.ensure_reg_or_pool(a1)
+ lr,lq = self.rm.ensure_even_odd_pair(a0, op, bind_first=True)
+ return [lr, lq, l1]
+
prepare_int_le = helper.generate_cmp_op()
prepare_int_lt = helper.generate_cmp_op()
prepare_int_ge = helper.generate_cmp_op()
diff --git a/rpython/jit/backend/zarch/test/test_int.py b/rpython/jit/backend/zarch/test/test_int.py
--- a/rpython/jit/backend/zarch/test/test_int.py
+++ b/rpython/jit/backend/zarch/test/test_int.py
@@ -35,41 +35,13 @@
fail = self.cpu.get_latest_descr(deadframe)
assert fail == finishdescr # ensures that guard is not taken!
- def test_double_evenodd_pair(self):
- code = """
- [i0]
- i1 = int_floordiv(i0, 2)
- i2 = int_floordiv(i0, 3)
- i3 = int_floordiv(i0, 4)
- i4 = int_floordiv(i0, 5)
- i5 = int_floordiv(i0, 6)
- i6 = int_floordiv(i0, 7)
- i7 = int_floordiv(i0, 8)
- i8 = int_le(i1, 0)
- guard_true(i8) [i1,i2,i3,i4,i5,i6,i7]
- finish(i0, descr=faildescr)
- """
- # the guard forces 3 spills because after 4 divisions
- # all even slots of the managed registers are full
- loop = parse(code, namespace={'faildescr': BasicFinalDescr(1)})
- looptoken = JitCellToken()
- self.cpu.compile_loop(loop.inputargs, loop.operations, looptoken)
- deadframe = self.cpu.execute_token(looptoken, 100)
- fail = self.cpu.get_latest_descr(deadframe)
- for i in range(2,9):
- assert self.cpu.get_int_value(deadframe, i-2) == 100//i
-
-
-
@py.test.mark.parametrize('value', [2,3,15,2**16])
def test_evenodd_pair_extensive(self, value):
instrs = []
failargs = []
values = []
j = 0
- mapping = (('int_floordiv',lambda x,y: x // y),
- ('int_mod', lambda x,y: x % y),
- ('int_mul_ovf', lambda x,y: x * y))
+ mapping = (('int_mul_ovf', lambda x,y: x * y),)
for i in range(20):
name, func = mapping[j]
instrs.append("i{d} = {i}(i0, {d})".format(d=i+1, i=name))
diff --git a/rpython/jit/backend/zarch/test/test_regalloc.py b/rpython/jit/backend/zarch/test/test_regalloc.py
--- a/rpython/jit/backend/zarch/test/test_regalloc.py
+++ b/rpython/jit/backend/zarch/test/test_regalloc.py
@@ -146,128 +146,3 @@
assert cpu.get_int_value(deadframe, 0) == 0
assert cpu.get_int_value(deadframe, 1) == -1000
-def test_bug_0():
- cpu, deadframe = run([-13, 10, 10, 8, -8, -16, -18, 46, -12, 26], '''
- [i1, i2, i3, i4, i5, i6, i7, i8, i9, i10]
- i11 = uint_gt(i3, -48)
- i12 = int_xor(i8, i1)
- i13 = int_gt(i6, -9)
- i14 = int_le(i13, i2)
- i15 = int_le(i11, i5)
- i16 = uint_ge(i13, i13)
- i17 = int_or(i9, -23)
- i18 = int_lt(i10, i13)
- i19 = int_or(i15, i5)
- i20 = int_xor(i17, 54)
- i21 = int_mul(i8, i10)
- i22 = int_or(i3, i9)
- i41 = int_and(i11, -4)
- i42 = int_or(i41, 1)
- i23 = int_mod(i12, i42)
- i24 = int_is_true(i6)
- i25 = uint_rshift(i15, 6)
- i26 = int_or(-4, i25)
- i27 = int_invert(i8)
- i28 = int_sub(-113, i11)
- i29 = int_neg(i7)
- i30 = int_neg(i24)
- i31 = int_floordiv(i3, 53)
- i32 = int_mul(i28, i27)
- i43 = int_and(i18, -4)
- i44 = int_or(i43, 1)
- i33 = int_mod(i26, i44)
- i34 = int_or(i27, i19)
- i35 = uint_lt(i13, 1)
- i45 = int_and(i21, 31)
- i36 = int_rshift(i21, i45)
- i46 = int_and(i20, 31)
- i37 = uint_rshift(i4, i46)
- i38 = uint_gt(i33, -11)
- i39 = int_neg(i7)
- i40 = int_gt(i24, i32)
- i99 = same_as_i(0)
- guard_true(i99) [i40, i36, i37, i31, i16, i34, i35, i23, i22, i29, i14, i39, i30, i38]
- finish(42)
- ''')
- assert cpu.get_int_value(deadframe, 0) == 0
- assert cpu.get_int_value(deadframe, 1) == 0
- assert cpu.get_int_value(deadframe, 2) == 0
- assert cpu.get_int_value(deadframe, 3) == 0
- assert cpu.get_int_value(deadframe, 4) == 1
- assert cpu.get_int_value(deadframe, 5) == -7
- assert cpu.get_int_value(deadframe, 6) == 1
- assert cpu.get_int_value(deadframe, 7) == 0
- assert cpu.get_int_value(deadframe, 8) == -2
- assert cpu.get_int_value(deadframe, 9) == 18
- assert cpu.get_int_value(deadframe, 10) == 1
- assert cpu.get_int_value(deadframe, 11) == 18
- assert cpu.get_int_value(deadframe, 12) == -1
- assert cpu.get_int_value(deadframe, 13) == 0
-
-def test_bug_1():
- cpu, deadframe = run([17, -20, -6, 6, 1, 13, 13, 9, 49, 8], '''
- [i1, i2, i3, i4, i5, i6, i7, i8, i9, i10]
- i11 = uint_lt(i6, 0)
- i41 = int_and(i3, 31)
- i12 = int_rshift(i3, i41)
- i13 = int_neg(i2)
- i14 = int_add(i11, i7)
- i15 = int_or(i3, i2)
- i16 = int_or(i12, i12)
- i17 = int_ne(i2, i5)
- i42 = int_and(i5, 31)
- i18 = uint_rshift(i14, i42)
- i43 = int_and(i14, 31)
- i19 = int_lshift(7, i43)
- i20 = int_neg(i19)
- i21 = int_mod(i3, 1)
- i22 = uint_ge(i15, i1)
- i44 = int_and(i16, 31)
- i23 = int_lshift(i8, i44)
- i24 = int_is_true(i17)
- i45 = int_and(i5, 31)
- i25 = int_lshift(i14, i45)
- i26 = int_lshift(i5, 17)
- i27 = int_eq(i9, i15)
- i28 = int_ge(0, i6)
- i29 = int_neg(i15)
- i30 = int_neg(i22)
- i31 = int_add(i7, i16)
- i32 = uint_lt(i19, i19)
- i33 = int_add(i2, 1)
- i34 = int_neg(i5)
- i35 = int_add(i17, i24)
- i36 = uint_lt(2, i16)
- i37 = int_neg(i9)
- i38 = int_gt(i4, i11)
- i39 = int_lt(i27, i22)
- i40 = int_neg(i27)
- i99 = same_as_i(0)
- guard_true(i99) [i40, i10, i36, i26, i13, i30, i21, i33, i18, i25, i31, i32, i28, i29, i35, i38, i20, i39, i34, i23, i37]
- finish(-42)
- ''')
- assert cpu.get_int_value(deadframe, 0) == 0
- assert cpu.get_int_value(deadframe, 1) == 8
- assert cpu.get_int_value(deadframe, 2) == 1
- assert cpu.get_int_value(deadframe, 3) == 131072
- assert cpu.get_int_value(deadframe, 4) == 20
- assert cpu.get_int_value(deadframe, 5) == -1
- assert cpu.get_int_value(deadframe, 6) == 0
- assert cpu.get_int_value(deadframe, 7) == -19
- assert cpu.get_int_value(deadframe, 8) == 6
- assert cpu.get_int_value(deadframe, 9) == 26
- assert cpu.get_int_value(deadframe, 10) == 12
- assert cpu.get_int_value(deadframe, 11) == 0
- assert cpu.get_int_value(deadframe, 12) == 0
- assert cpu.get_int_value(deadframe, 13) == 2
- assert cpu.get_int_value(deadframe, 14) == 2
- assert cpu.get_int_value(deadframe, 15) == 1
- assert cpu.get_int_value(deadframe, 16) == -57344
- assert cpu.get_int_value(deadframe, 17) == 1
- assert cpu.get_int_value(deadframe, 18) == -1
- if WORD == 4:
- assert cpu.get_int_value(deadframe, 19) == -2147483648
- elif WORD == 8:
- assert cpu.get_int_value(deadframe, 19) == 19327352832
- assert cpu.get_int_value(deadframe, 20) == -49
-
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