[pypy-commit] pypy s390x-backend: replaced load 32bit imm with load imm that can handle 64 bit too

[plan_rich]

Author: Richard Plangger <planrichi at gmail.com>
Branch: s390x-backend
Changeset: r81834:045f28548d0a
Date: 2016-01-18 13:51 +0100
http://bitbucket.org/pypy/pypy/changeset/045f28548d0a/

Log:	replaced load 32bit imm with load imm that can handle 64 bit too

diff --git a/rpython/jit/backend/zarch/assembler.py b/rpython/jit/backend/zarch/assembler.py
--- a/rpython/jit/backend/zarch/assembler.py
+++ b/rpython/jit/backend/zarch/assembler.py
@@ -1227,8 +1227,7 @@
             gcmap = lltype.nullptr(jitframe.GCMAP)
         self.load_gcmap(self.mc, r.r2, gcmap)
 
-        assert fail_descr_loc.getint() <= 2**32-1
-        self.mc.LGFI(r.r3, fail_descr_loc)
+        self.mc.load_imm(r.r3, fail_descr_loc.getint())
         self.mc.STG(r.r3, l.addr(ofs, r.SPP))
         self.mc.STG(r.r2, l.addr(ofs2, r.SPP))
 
diff --git a/rpython/jit/backend/zarch/opassembler.py b/rpython/jit/backend/zarch/opassembler.py
--- a/rpython/jit/backend/zarch/opassembler.py
+++ b/rpython/jit/backend/zarch/opassembler.py
@@ -694,16 +694,19 @@
 
     def _cmp_guard_class(self, op, locs, regalloc):
         offset = self.cpu.vtable_offset
+        loc_ptr = locs[0]
+        loc_classptr = locs[1]
         if offset is not None:
             # could be one instruction shorter, but don't care because
             # it's not this case that is commonly translated
-            self.mc.LG(r.SCRATCH, l.addr(offset, locs[0]))
+            self.mc.LG(r.SCRATCH, l.addr(offset, loc_ptr))
             self.mc.load_imm(r.SCRATCH2, locs[1].value)
             self.mc.cmp_op(r.SCRATCH, r.SCRATCH2)
         else:
+            classptr = loc_classptr.value
             expected_typeid = (self.cpu.gc_ll_descr
-                    .get_typeid_from_classptr_if_gcremovetypeptr(locs[1].value))
-            self._cmp_guard_gc_type(locs[0], expected_typeid)
+                    .get_typeid_from_classptr_if_gcremovetypeptr(classptr))
+            self._cmp_guard_gc_type(loc_ptr, expected_typeid)
 
     def _read_typeid(self, targetreg, loc_ptr):
         # Note that the typeid half-word is at offset 0 on a little-endian
@@ -753,10 +756,10 @@
         offset2 = self.cpu.subclassrange_min_offset
         if offset is not None:
             # read this field to get the vtable pointer
-            self.mc.LG(r.SCRATCH2, l.addr(offset, loc_object))
+            self.mc.LG(r.SCRATCH, l.addr(offset, loc_object))
             # read the vtable's subclassrange_min field
             assert check_imm_value(offset2)
-            self.mc.load(r.SCRATCH2, r.SCRATCH2, offset2)
+            self.mc.load(r.SCRATCH2, r.SCRATCH, offset2)
         else:
             # read the typeid
             self._read_typeid(r.SCRATCH, loc_object)
diff --git a/rpython/jit/backend/zarch/regalloc.py b/rpython/jit/backend/zarch/regalloc.py
--- a/rpython/jit/backend/zarch/regalloc.py
+++ b/rpython/jit/backend/zarch/regalloc.py
@@ -1081,6 +1081,11 @@
         arglocs = self._prepare_guard(op, [loc, resloc])
         return arglocs
 
+    def prepare_guard_is_object(self, op):
+        loc_object = self.ensure_reg(op.getarg(0), force_in_reg=True)
+        arglocs = self._prepare_guard(op, [loc_object])
+        return arglocs
+
     def prepare_save_exception(self, op):
         res = self.rm.force_allocate_reg(op)
         return [res]
@@ -1191,6 +1196,7 @@
         # we know it does not move, but well
         rgc._make_sure_does_not_move(fail_descr)
         fail_descr = rffi.cast(lltype.Signed, fail_descr)
+        assert fail_descr > 0
         if op.numargs() > 0:
             loc = self.ensure_reg(op.getarg(0))
             locs = [loc, imm(fail_descr)]