[pypy-commit] pypy fix-longevity: (plan_rich, remi) possibly silghtly improve corner case

[Raemi]

Author: Remi Meier <remi.meier at gmail.com>
Branch: fix-longevity
Changeset: r82518:ff9c442e6dc8
Date: 2016-02-25 17:43 +0100
http://bitbucket.org/pypy/pypy/changeset/ff9c442e6dc8/

Log:	(plan_rich,remi) possibly silghtly improve corner case

diff --git a/rpython/jit/backend/llsupport/regalloc.py b/rpython/jit/backend/llsupport/regalloc.py
--- a/rpython/jit/backend/llsupport/regalloc.py
+++ b/rpython/jit/backend/llsupport/regalloc.py
@@ -667,11 +667,22 @@
             # we need to find a new place for variable v and
             # store result in the same place
 
-            loc = self.reg_bindings[v]
-            # only spill variable is allowed to reassign a new register to a live range
-            result_loc = self.force_allocate_reg(result_v, forbidden_vars=forbidden_vars)
-            self.assembler.regalloc_mov(loc, result_loc)
-            loc = result_loc
+            if (not self.has_free_registers()
+                and self._pick_variable_to_spill(None, forbidden_vars) is v):
+                # if we would be chosen for spilling, we give up our register
+                # for result_v (and move us away onto the frame) instead of
+                # forcing a spill of some other variable.
+                loc = self.reg_bindings[v]
+                del self.reg_bindings[v]
+                if self.frame_manager.get(v) is None:
+                    self._move_variable_away(v, loc)
+                self.reg_bindings[result_v] = loc
+            else:
+                loc = self.reg_bindings[v]
+                # only spill variable is allowed to reassign a new register to a live range
+                result_loc = self.force_allocate_reg(result_v, forbidden_vars=forbidden_vars)
+                self.assembler.regalloc_mov(loc, result_loc)
+                loc = result_loc
 
 
             #del self.reg_bindings[v]
diff --git a/rpython/jit/backend/x86/regalloc.py b/rpython/jit/backend/x86/regalloc.py
--- a/rpython/jit/backend/x86/regalloc.py
+++ b/rpython/jit/backend/x86/regalloc.py
@@ -62,14 +62,22 @@
     save_around_call_regs = abi_param_regs + [eax, edx, r10]
 
     def get_abi_param_register(self, i):
-        assert i >= 0 and i < len(self.abi_param_regs)
-        return self.abi_param_regs[i]
+        if not IS_X86_32 and 0 <= i < len(self.abi_param_regs):
+            return self.abi_param_regs[i]
+        return None
+
 
 class X86XMMRegisterManager(RegisterManager):
     box_types = [FLOAT, INT] # yes INT!
     all_regs = [xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7]
     # we never need lower byte I hope
     save_around_call_regs = all_regs
+    abi_param_regs = all_regs
+
+    def get_abi_param_register(self, i):
+        if not IS_X86_32 and 0 <= i < len(self.abi_param_regs):
+            return self.abi_param_regs[i]
+        return None
 
     def convert_to_imm(self, c):
         adr = self.assembler.datablockwrapper.malloc_aligned(8, 8)