[pypy-commit] pypy fix-longevity: (plan_rich, remi) fix for updating bridge argument register assignment

[Raemi]

Author: Remi Meier <remi.meier at gmail.com>
Branch: fix-longevity
Changeset: r82512:af0b03bc7ce0
Date: 2016-02-25 16:46 +0100
http://bitbucket.org/pypy/pypy/changeset/af0b03bc7ce0/

Log:	(plan_rich,remi) fix for updating bridge argument register
	assignment

diff --git a/rpython/jit/backend/llsupport/regalloc.py b/rpython/jit/backend/llsupport/regalloc.py
--- a/rpython/jit/backend/llsupport/regalloc.py
+++ b/rpython/jit/backend/llsupport/regalloc.py
@@ -803,7 +803,6 @@
         self.longevity[var] = (start, end)
 
     def get_call_argument_index(self, var, pos):
-        assert self.dist_to_next_call[pos] >= 0
         dist_to_call = self.dist_to_next_call[pos]
         if dist_to_call < 0:
             return -1
diff --git a/rpython/jit/backend/x86/regalloc.py b/rpython/jit/backend/x86/regalloc.py
--- a/rpython/jit/backend/x86/regalloc.py
+++ b/rpython/jit/backend/x86/regalloc.py
@@ -274,6 +274,7 @@
     def _update_bindings(self, arglocs, inputargs):
         # XXX this should probably go to llsupport/regalloc.py
         used = set()
+        used_xmm = set()
         i = 0
         # manually set the register and frame bindings for
         # all inputargs (for a bridge)
@@ -285,7 +286,7 @@
             if isinstance(loc, RegLoc):
                 if arg.type == FLOAT:
                     self.xrm.reg_bindings[arg] = loc
-                    used.add(loc)
+                    used_xmm.add(loc)
                 else:
                     if loc is ebp:
                         self.rm.bindings_to_frame_reg[arg] = None
@@ -296,7 +297,7 @@
                 self.fm.bind(arg, loc)
         #
         self.rm.update_free_registers(used)
-        self.xrm.update_free_registers(used)
+        self.xrm.update_free_registers(used_xmm)
         self.possibly_free_vars(list(inputargs))
         self.fm.finish_binding()
         self.rm._check_invariants()