[pypy-commit] pypy s390x-backend: some more fixes, wrong offset was calculated by push/pop to jit frame

[plan_rich]

Author: Richard Plangger <planrichi at gmail.com>
Branch: s390x-backend
Changeset: r82319:705395ae74a3
Date: 2016-02-18 15:16 +0100
http://bitbucket.org/pypy/pypy/changeset/705395ae74a3/

Log:	some more fixes, wrong offset was calculated by push/pop to jit
	frame

diff --git a/rpython/jit/backend/zarch/assembler.py b/rpython/jit/backend/zarch/assembler.py
--- a/rpython/jit/backend/zarch/assembler.py
+++ b/rpython/jit/backend/zarch/assembler.py
@@ -182,7 +182,7 @@
         RCS2 = r.r10
         RCS3 = r.r11
 
-        # r10,r11,r12,r2,f0 -> makes exactly 4 words + 8 byte
+        # r9,r10,r11,r2,f0 -> makes exactly 4 words + 8 byte
         extra_stack_size = 4 * WORD + 8
         if for_frame:
             # NOTE: don't save registers on the jitframe here!  It might
@@ -201,7 +201,7 @@
             mc.LG(r.SCRATCH, l.addr(0, r.SP))
             mc.STG(r.SCRATCH, l.addr(-extra_stack_size, r.SP))
             mc.LAY(r.SP, l.addr(-extra_stack_size, r.SP))
-            mc.STMG(r.r10, r.r12, l.addr(off, r.SP))
+            mc.STMG(r.r9, r.r11, l.addr(off, r.SP))
             mc.STG(r.r2, l.addr(off+3*WORD, r.SP))
             # OK to use STD, because offset is not negative
             mc.STD(r.f0, l.addr(off+4*WORD, r.SP))
@@ -253,7 +253,7 @@
 
         if for_frame:
             off = STD_FRAME_SIZE_IN_BYTES
-            mc.LMG(r.r10, r.r12, l.addr(off, r.SP))
+            mc.LMG(r.r9, r.r11, l.addr(off, r.SP))
             mc.LG(r.r2, l.addr(off+3*WORD, r.SP))
             mc.LD(r.f0, l.addr(off+4*WORD, r.SP))
             mc.LAY(r.SP, l.addr(extra_stack_size, r.SP))
@@ -418,7 +418,6 @@
         if supports_floats:
             self._push_fp_regs_to_jitframe(mc)
 
-        # allocate a stack frame!
         mc.raw_call(r.r11)
 
         # Finish
@@ -1092,7 +1091,8 @@
         base_ofs = self.cpu.get_baseofs_of_frame_field()
         if len(includes) == 1:
             iv = includes[0]
-            addr = l.addr(base_ofs + iv.value * WORD, r.SPP)
+            v = r.ALL_REG_INDEXES[iv]
+            addr = l.addr(base_ofs + v * WORD, r.SPP)
             if store:
                 mc.STG(iv, addr)
             else:
diff --git a/rpython/jit/backend/zarch/locations.py b/rpython/jit/backend/zarch/locations.py
--- a/rpython/jit/backend/zarch/locations.py
+++ b/rpython/jit/backend/zarch/locations.py
@@ -75,8 +75,8 @@
     def is_fp_reg(self):
         return True
 
-    def as_key(self):            # 20 <= as_key <= 35
-        return self.value + 20
+    def as_key(self):            # 16 <= as_key <= 32
+        return self.value + 16
 
     def is_float(self):
         return True
@@ -125,34 +125,11 @@
         return True
 
     def as_key(self):                # an aligned word + 10000
-        return self.position + 10000
+        return -self.position + 10000
 
     def is_float(self):
         return self.type == FLOAT
 
-class RawSPStackLocation(AssemblerLocation):
-    _immutable_ = True
-
-    def __init__(self, sp_offset, type=INT):
-        if type == FLOAT:
-            self.width = DOUBLE_WORD
-        else:
-            self.width = WORD
-        self.value = sp_offset
-        self.type = type
-
-    def __repr__(self):
-        return 'SP(%s)+%d' % (self.type, self.value,)
-
-    def is_raw_sp(self):
-        return True
-
-    def is_float(self):
-        return self.type == FLOAT
-
-    def as_key(self):            # a word >= 1000, and < 1000 + size of SP frame
-        return self.value + 1000
-
 class AddressLocation(AssemblerLocation):
     _immutable_ = True
 
@@ -173,9 +150,6 @@
         if length:
             self.length = length.value
 
-    def as_key(self):
-        return self.displace + 100000
-
 class PoolLoc(AddressLocation):
     _immutable_ = True
     width = WORD
@@ -205,6 +179,9 @@
     def __repr__(self):
         return "pool(i,%d)" %  self.displace
 
+    def as_key(self):
+        return -self.displace // 8 + 20000
+
 def addr(displace, basereg=None, indexreg=None, length=None):
     return AddressLocation(basereg, indexreg, displace, length)
 
diff --git a/rpython/jit/backend/zarch/opassembler.py b/rpython/jit/backend/zarch/opassembler.py
--- a/rpython/jit/backend/zarch/opassembler.py
+++ b/rpython/jit/backend/zarch/opassembler.py
@@ -404,8 +404,8 @@
         if regalloc.fprm.reg_bindings:
             floats = True
         cond_call_adr = self.cond_call_slowpath[floats * 2 + callee_only]
-        self.mc.load_imm(r.SCRATCH, cond_call_adr)
-        self.mc.BASR(r.RETURN, r.SCRATCH)
+        self.mc.load_imm(r.r14, cond_call_adr)
+        self.mc.BASR(r.r14, r.r14)
         # restoring the registers saved above, and doing pop_gcmap(), is left
         # to the cond_call_slowpath helper.  We never have any result value.
         relative_target = self.mc.currpos() - jmp_adr
diff --git a/rpython/jit/backend/zarch/registers.py b/rpython/jit/backend/zarch/registers.py
--- a/rpython/jit/backend/zarch/registers.py
+++ b/rpython/jit/backend/zarch/registers.py
@@ -38,7 +38,9 @@
     ALL_REG_INDEXES[_r] = len(ALL_REG_INDEXES)
 for _r in MANAGED_FP_REGS:
     ALL_REG_INDEXES[_r] = len(ALL_REG_INDEXES)
-JITFRAME_FIXED_SIZE = len(ALL_REG_INDEXES) + 1 # plus one word to have an even number
+# NOT used, but keeps JITFRAME_FIXED_SIZE even
+ALL_REG_INDEXES[f15] = len(ALL_REG_INDEXES)
+JITFRAME_FIXED_SIZE = len(ALL_REG_INDEXES)
 
 def odd_reg(r):
     assert r.value % 2 == 0