[pypy-commit] pypy s390x-backend: syscall write working properly. string put into literal pool
plan_rich
noreply at buildbot.pypy.org
Wed Oct 21 15:35:30 EDT 2015
Author: Richard Plangger <planrichi at gmail.com>
Branch: s390x-backend
Changeset: r80380:6ad3bdfddaa3
Date: 2015-10-21 14:42 +0200
http://bitbucket.org/pypy/pypy/changeset/6ad3bdfddaa3/
Log: syscall write working properly. string put into literal pool
diff --git a/rpython/jit/backend/zarch/instruction_builder.py b/rpython/jit/backend/zarch/instruction_builder.py
--- a/rpython/jit/backend/zarch/instruction_builder.py
+++ b/rpython/jit/backend/zarch/instruction_builder.py
@@ -84,6 +84,13 @@
byte = displace >> 12 & 0xff
mc.writechar(chr(byte))
+def build_i(mnemonic, (opcode,)):
+ @builder.arguments('u8')
+ def encode_i(self, imm):
+ self.writechar(opcode)
+ self.writechar(chr(imm))
+ return encode_i
+
def build_rr(mnemonic, (opcode,)):
@builder.arguments('r,r')
def encode_rr(self, reg1, reg2):
diff --git a/rpython/jit/backend/zarch/instructions.py b/rpython/jit/backend/zarch/instructions.py
--- a/rpython/jit/backend/zarch/instructions.py
+++ b/rpython/jit/backend/zarch/instructions.py
@@ -77,6 +77,7 @@
'SRP': ('ssc', ['\xF0']),
'MVCK': ('ssd', ['\xD9']),
+ 'LA': ('rx', ['\x41']),
'LAY': ('rxy', ['\xE3','\x71']),
'LMD': ('sse', ['\xEF']),
'LMG': ('rsy', ['\xEB','\x04']),
@@ -87,6 +88,8 @@
'PKA': ('ssf', ['\xE9']),
'STMG': ('rsy', ['\xEB','\x24']),
+
+ 'SVC': ('i', ['\x0A']),
}
all_mnemonic_codes.update(arith_mnemonic_codes)
all_mnemonic_codes.update(logic_mnemonic_codes)
diff --git a/rpython/jit/backend/zarch/test/test_assembler.py b/rpython/jit/backend/zarch/test/test_assembler.py
--- a/rpython/jit/backend/zarch/test/test_assembler.py
+++ b/rpython/jit/backend/zarch/test/test_assembler.py
@@ -123,7 +123,6 @@
return ctxmgr()
def patch_branch_imm16(self, base, imm):
- print "branch to", imm, "base", base, self.cur(), self.pos('lit.end'), self.pos('lit')
imm = (imm & 0xffff) >> 1
self.mc.overwrite(base, chr((imm >> 8) & 0xFF))
self.mc.overwrite(base+1, chr(imm & 0xFF))
@@ -141,7 +140,6 @@
def jump_to(self, reg, label):
val = (self.pos(label) - self.cur())
- print "val", val
self.mc.BRAS(reg, loc.imm(val))
def test_stmg(self):
@@ -172,3 +170,17 @@
self.a.jmpto(reg.r14)
assert run_asm(self.a) == 120
+ def test_printf(self):
+ with self.label('func', func=True):
+ with self.label('lit'):
+ self.mc.BRAS(reg.r13, loc.imm(0))
+ for c in "hello syscall\n":
+ self.mc.writechar(c)
+ self.jump_here(self.mc.BRAS, 'lit')
+ self.mc.LGHI(reg.r2, loc.imm(1)) # stderr
+ self.mc.LA(reg.r3, loc.addr(0, reg.r13)) # char*
+ self.mc.LGHI(reg.r4, loc.imm(14)) # length
+ # write sys call
+ self.mc.SVC(loc.imm(4))
+ self.a.jmpto(reg.r14)
+ assert run_asm(self.a) == 14
More information about the pypy-commit
mailing list