[pypy-commit] pypy s390x-backend: added the right parameters to obj dump and added test regex for compile_asm_len
plan_rich
noreply at buildbot.pypy.org
Tue Nov 24 05:50:16 EST 2015
Author: Richard Plangger <planrichi at gmail.com>
Branch: s390x-backend
Changeset: r80882:ab489b42ecd2
Date: 2015-11-24 11:50 +0100
http://bitbucket.org/pypy/pypy/changeset/ab489b42ecd2/
Log: added the right parameters to obj dump and added test regex for
compile_asm_len
diff --git a/rpython/jit/backend/llsupport/jump.py b/rpython/jit/backend/llsupport/jump.py
--- a/rpython/jit/backend/llsupport/jump.py
+++ b/rpython/jit/backend/llsupport/jump.py
@@ -64,18 +64,16 @@
assert pending_dests == 0
def _move(assembler, src, dst, tmpreg):
- if dst.is_stack() and src.is_stack():
- assembler.regalloc_mov(src, tmpreg)
- src = tmpreg
+ # some assembler cannot handle memory to memory moves without
+ # a tmp register, thus prepare src according to the ISA capabilities
+ src = assembler.regalloc_prepare_move(src, dst, tmpreg)
assembler.regalloc_mov(src, dst)
def remap_frame_layout_mixed(assembler,
src_locations1, dst_locations1, tmpreg1,
- src_locations2, dst_locations2, tmpreg2):
+ src_locations2, dst_locations2, tmpreg2, WORD):
# find and push the fp stack locations from src_locations2 that
# are going to be overwritten by dst_locations1
- # TODO
- from rpython.jit.backend.zarch.arch import WORD
extrapushes = []
dst_keys = {}
for loc in dst_locations1:
diff --git a/rpython/jit/backend/tool/viewcode.py b/rpython/jit/backend/tool/viewcode.py
--- a/rpython/jit/backend/tool/viewcode.py
+++ b/rpython/jit/backend/tool/viewcode.py
@@ -51,11 +51,13 @@
'arm_32': 'arm',
'ppc' : 'powerpc:common64',
'ppc-64' : 'powerpc:common64',
+ 's390x': 's390:64-bit',
}
machine_endianness = {
# default value: 'little'
'ppc' : sys.byteorder, # i.e. same as the running machine...
'ppc-64' : sys.byteorder, # i.e. same as the running machine...
+ 's390x' : sys.byteorder, # i.e. same as the running machine...
}
cmd = find_objdump()
objdump = ('%(command)s -b binary -m %(machine)s '
diff --git a/rpython/jit/backend/zarch/assembler.py b/rpython/jit/backend/zarch/assembler.py
--- a/rpython/jit/backend/zarch/assembler.py
+++ b/rpython/jit/backend/zarch/assembler.py
@@ -414,6 +414,15 @@
self.mc.LG(r.SCRATCH, l.addr(index, r.SP))
self.regalloc_mov(r.SCRATCH, loc)
+ def regalloc_prepare_move(self, src, dst, tmp):
+ if dst.is_stack() and src.is_stack():
+ self.regalloc_mov(src, tmp)
+ return tmp
+ if dst.is_stack() and src.is_in_pool():
+ self.regalloc_mov(src, tmp)
+ return tmp
+ return src
+
def _assemble(self, regalloc, inputargs, operations):
self._regalloc = regalloc
self.guard_success_cc = c.cond_none
@@ -441,18 +450,18 @@
elif loc.is_stack():
with scratch_reg(self.mc):
offset = loc.value
- self.mc.load_imm(r.SCRATCH, value)
- self.mc.store(r.SCRATCH.value, r.SPP, offset)
+ self.mc.load_imm(r.SCRATCH, prev_loc)
+ self.mc.STG(r.SCRATCH, l.addr(offset, r.SPP))
return
assert 0, "not supported location"
elif prev_loc.is_in_pool():
if loc.is_reg():
self.mc.LG(loc, prev_loc)
+ return
elif loc.is_fp_reg():
self.mc.LD(loc, prev_loc)
- else:
- xxx
- return
+ return
+ assert 0, "not supported location (previous is pool loc)"
elif prev_loc.is_stack():
offset = prev_loc.value
# move from memory to register
diff --git a/rpython/jit/backend/zarch/locations.py b/rpython/jit/backend/zarch/locations.py
--- a/rpython/jit/backend/zarch/locations.py
+++ b/rpython/jit/backend/zarch/locations.py
@@ -194,6 +194,9 @@
if length:
self.length = length.value
+ def as_key(self):
+ return self.displace + 100000
+
class PoolLoc(AddressLocation):
_immutable_ = True
width = WORD
@@ -218,7 +221,6 @@
def __repr__(self):
return "pool(i,%d)" % self.displace
-
def addr(displace, basereg=None, indexreg=None, length=None):
return AddressLocation(basereg, indexreg, displace, length)
diff --git a/rpython/jit/backend/zarch/opassembler.py b/rpython/jit/backend/zarch/opassembler.py
--- a/rpython/jit/backend/zarch/opassembler.py
+++ b/rpython/jit/backend/zarch/opassembler.py
@@ -251,12 +251,12 @@
if l0.is_reg():
if l1.is_imm():
- self.mc.cmp_op(0, l0.value, l1.getint(), imm=True)
+ self.mc.cmp_op(l0, l1, imm=True)
else:
- self.mc.cmp_op(0, l0.value, l1.value)
+ self.mc.cmp_op(l0, l1)
elif l0.is_fp_reg():
assert l1.is_fp_reg()
- self.mc.cmp_op(0, l0.value, l1.value, fp=True)
+ self.mc.cmp_op(l0, l1, fp=True)
self.guard_success_cc = c.EQ
self._emit_guard(op, failargs)
diff --git a/rpython/jit/backend/zarch/regalloc.py b/rpython/jit/backend/zarch/regalloc.py
--- a/rpython/jit/backend/zarch/regalloc.py
+++ b/rpython/jit/backend/zarch/regalloc.py
@@ -570,9 +570,9 @@
if box.type == FLOAT:
return self.fprm.ensure_reg(box)
else:
- if check_imm_box(box):
+ if helper.check_imm(box):
return imm(box.getint())
- return self.rm.ensure_reg(box)
+ return self.rm.ensure_reg(box, force_in_reg=True)
def ensure_reg_or_any_imm(self, box):
if box.type == FLOAT:
@@ -580,7 +580,7 @@
else:
if isinstance(box, Const):
return imm(box.getint())
- return self.rm.ensure_reg(box)
+ return self.rm.ensure_reg(box, force_in_reg=True)
def get_scratch_reg(self, type):
if type == FLOAT:
@@ -759,6 +759,12 @@
prepare_guard_overflow = prepare_guard_no_exception
prepare_guard_not_forced = prepare_guard_no_exception
+ def prepare_guard_value(self, op):
+ l0 = self.ensure_reg(op.getarg(0))
+ l1 = self.ensure_reg_or_16bit_imm(op.getarg(1))
+ arglocs = self._prepare_guard(op, [l0, l1])
+ return arglocs
+
def prepare_label(self, op):
descr = op.getdescr()
assert isinstance(descr, TargetToken)
@@ -838,7 +844,7 @@
remap_frame_layout_mixed(self.assembler,
src_locations1, dst_locations1, tmploc,
- src_locations2, dst_locations2, fptmploc)
+ src_locations2, dst_locations2, fptmploc, WORD)
return []
def prepare_finish(self, op):
diff --git a/rpython/jit/backend/zarch/test/test_runner.py b/rpython/jit/backend/zarch/test/test_runner.py
--- a/rpython/jit/backend/zarch/test/test_runner.py
+++ b/rpython/jit/backend/zarch/test/test_runner.py
@@ -23,3 +23,7 @@
cpu = CPU_S390_64(rtyper=None, stats=FakeStats())
cpu.setup_once()
return cpu
+
+ # TODO verify: the lgr might be redundant!
+ add_loop_instructions = "lg; lgr; larl; agr; cgfi; je; j;$"
+ bridge_loop_instructions = ("larl; lg; br;")
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