[pypy-commit] pypy s390x-backend: ironed out a problem in prepare unary op

[plan_rich]

Author: Richard Plangger <planrichi at gmail.com>
Branch: s390x-backend
Changeset: r80756:7f5ca8a6eb21
Date: 2015-11-18 15:27 +0100
http://bitbucket.org/pypy/pypy/changeset/7f5ca8a6eb21/

Log:	ironed out a problem in prepare unary op

diff --git a/rpython/jit/backend/zarch/opassembler.py b/rpython/jit/backend/zarch/opassembler.py
--- a/rpython/jit/backend/zarch/opassembler.py
+++ b/rpython/jit/backend/zarch/opassembler.py
@@ -114,25 +114,23 @@
             #self.mc.AGR(lr, l1)
 
     def emit_int_invert(self, op, arglocs, regalloc):
-        l0, l1 = arglocs
+        l0, _ = arglocs
         assert not l0.is_imm()
-        self.mc.XG(l1, l.pool(self.pool.constant_64_ones))
-        if l0 != l1:
-            self.mc.LGR(l0, l1)
+        self.mc.XG(l0, l.pool(self.pool.constant_64_ones))
 
     def emit_int_neg(self, op, arglocs, regalloc):
-        l0, l1 = arglocs
-        self.mc.LCGR(l0, l1)
+        l0, _ = arglocs
+        self.mc.LCGR(l0, l0)
 
     def emit_int_is_zero(self, op, arglocs, regalloc):
-        l0, l1 = arglocs
-        self.mc.CGHI(l1, l.imm(0))
-        self.flush_cc(c.EQ, l0)
+        l0, res = arglocs
+        self.mc.CGHI(l0, l.imm(0))
+        self.flush_cc(c.EQ, res)
 
     def emit_int_is_true(self, op, arglocs, regalloc):
-        l0, l1 = arglocs
+        l0, res = arglocs
         self.mc.CGHI(l0, l.imm(0))
-        self.flush_cc(c.NE, l0)
+        self.flush_cc(c.NE, res)
 
     emit_int_and = gen_emit_rr_or_rpool("NGR", "NG")
     emit_int_or  = gen_emit_rr_or_rpool("OGR", "OG")
diff --git a/rpython/jit/backend/zarch/regalloc.py b/rpython/jit/backend/zarch/regalloc.py
--- a/rpython/jit/backend/zarch/regalloc.py
+++ b/rpython/jit/backend/zarch/regalloc.py
@@ -431,6 +431,8 @@
             return r.SPP
         else:
             # else, return a regular register (not SPP).
+            if self.rm.reg_bindings.get(var, None) != None:
+                return self.rm.loc(var, must_exist=True)
             return self.rm.force_allocate_reg(var)
 
     def walk_operations(self, inputargs, operations):