[pypy-commit] pypy s390x-backend: saving the last used constant pool below the stack pointer

[plan_rich]

Author: Richard Plangger <planrichi at gmail.com>
Branch: s390x-backend
Changeset: r80516:2e5796108f90
Date: 2015-11-03 17:50 +0100
http://bitbucket.org/pypy/pypy/changeset/2e5796108f90/

Log:	saving the last used constant pool below the stack pointer

diff --git a/rpython/jit/backend/zarch/arch.py b/rpython/jit/backend/zarch/arch.py
--- a/rpython/jit/backend/zarch/arch.py
+++ b/rpython/jit/backend/zarch/arch.py
@@ -5,17 +5,19 @@
 #                                                 OFFSET
 #     +------------------------------+            0
 #     |  gpr save are (int+float)    |
-#     +------------------------------+            8
-#     |  local vars                  |
-#     +------------------------------+            0
+#     +------------------------------+            GPR_STACK_SAVE_IN_BYTES | 120
+#     |  last base pointer           |
+#     +------------------------------+            BSP_STACK_OFFSET        | 128
 #     |                              |
 #     +------------------------------+
 #     |                              |
-#     +------------------------------+ <- SP      0         (r15)
+#     +------------------------------+                                    | 140
+#
 #
 
 GPR_STACK_SAVE_IN_BYTES = 120
 STD_FRAME_SIZE_IN_BYTES = 140
+BSP_STACK_OFFSET = 128
 THREADLOCAL_ADDR_OFFSET = 8
 
 assert STD_FRAME_SIZE_IN_BYTES % 2 == 0
diff --git a/rpython/jit/backend/zarch/assembler.py b/rpython/jit/backend/zarch/assembler.py
--- a/rpython/jit/backend/zarch/assembler.py
+++ b/rpython/jit/backend/zarch/assembler.py
@@ -517,9 +517,10 @@
         # Build a new stackframe of size STD_FRAME_SIZE_IN_BYTES
         self.mc.STMG(r.r6, r.r15, l.addr(-GPR_STACK_SAVE_IN_BYTES, r.SP))
         self.mc.AGHI(r.SP, l.imm(-STD_FRAME_SIZE_IN_BYTES))
+        self.mc.LGR(r.BSP, r.SP)
 
         # save r4, the second argument, to THREADLOCAL_ADDR_OFFSET
-        self.mc.STG(r.r3, l.addr(THREADLOCAL_ADDR_OFFSET, r.SP))
+        #self.mc.STG(r.r3, l.addr(THREADLOCAL_ADDR_OFFSET, r.SP))
 
         # move the first argument to SPP: the jitframe object
         self.mc.LGR(r.SPP, r.r2)
@@ -579,7 +580,10 @@
         else:
             # restore the pool address
             offset = self.pool.get_descr_offset(descr)
-            self.mc.b_abs(l.pool(offset), restore_pool=True)
+            self.mc.LG(r.SCRATCH, l.pool(offset))
+            self.mc.LG(r.POOL, l.addr(0, r.BSP))
+            self.mc.AGHI(r.BSP, l.imm(8))
+            self.mc.BCR(c.ANY, r.SCRATCH)
             print "writing", hex(descr._ll_loop_code)
             self.pool.overwrite_64(self.mc, offset, descr._ll_loop_code)
 
diff --git a/rpython/jit/backend/zarch/codebuilder.py b/rpython/jit/backend/zarch/codebuilder.py
--- a/rpython/jit/backend/zarch/codebuilder.py
+++ b/rpython/jit/backend/zarch/codebuilder.py
@@ -117,11 +117,6 @@
         offset = reladdr - self.get_relative_pos()
         self.BRC(c.ANY, l.imm(offset))
 
-    def b_abs(self, pooled, restore_pool=False):
-        self.LG(r.r10, pooled)
-        self.LG(r.POOL, l.pool(0))
-        self.BCR(c.ANY, r.r10)
-
     def reserve_guard_branch(self):
         print "reserve!", self.get_relative_pos()
         self.BRC(l.imm(0x0), l.imm(0))
diff --git a/rpython/jit/backend/zarch/pool.py b/rpython/jit/backend/zarch/pool.py
--- a/rpython/jit/backend/zarch/pool.py
+++ b/rpython/jit/backend/zarch/pool.py
@@ -52,7 +52,7 @@
         self.size = 0
         self.offset_map.clear()
 
-    def pre_assemble(self, asm, operations, bridge=True):
+    def pre_assemble(self, asm, operations, bridge=False):
         self.reset()
         # O(len(operations)). I do not think there is a way
         # around this.
@@ -68,25 +68,24 @@
         # the current solution (gcc does the same), use a literal pool
         # located at register r13. This one can easily offset with 20
         # bit signed values (should be enough)
-        if bridge:
-            self.reserve_literal(8)
         for op in operations:
             self.ensure_can_hold_constants(asm, op)
         if self.size == 0:
             # no pool needed!
             return
-        self.size += 8
         assert self.size % 2 == 0
         #if self.size % 2 == 1:
         #    self.size += 1
-        assert self.size < 2**16-1
+        jump_offset = self.size+asm.mc.BRAS_byte_count
+        assert jump_offset < 2**15-1
         if bridge:
-            asm.mc.LGR(r.SCRATCH, r.r13)
-        asm.mc.BRAS(r.POOL, l.imm(self.size+asm.mc.BRAS_byte_count))
+            asm.mc.LGR(r.SCRATCH, r.POOL)
+        asm.mc.BRAS(r.POOL, l.imm(jump_offset))
         self.pool_start = asm.mc.get_relative_pos()
         asm.mc.write('\xFF' * self.size)
         if bridge:
-            asm.mc.STG(r.SCRATCH, l.pool(0))
+            asm.mc.STG(r.SCRATCH, l.addr(-8, r.BSP))
+            asm.mc.AGHI(r.BSP, l.imm(-8))
         print "pool with %d quad words" % (self.size // 8)
 
     def overwrite_64(self, mc, index, value):
diff --git a/rpython/jit/backend/zarch/registers.py b/rpython/jit/backend/zarch/registers.py
--- a/rpython/jit/backend/zarch/registers.py
+++ b/rpython/jit/backend/zarch/registers.py
@@ -7,13 +7,14 @@
 [r0,r1,r2,r3,r4,r5,r6,r7,r8,
  r9,r10,r11,r12,r13,r14,r15] = registers
 
-MANAGED_REGS = [r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10]
+MANAGED_REGS = [r0,r2,r3,r4,r5,r6,r7,r8,r9,r10]
 VOLATILES = [r6,r7,r8,r9,r10]
 SP = r15
+BSP = r12
 RETURN = r14
 POOL = r13
 SPP = r11
-SCRATCH = r12
+SCRATCH = r1
 
 [f0,f1,f2,f3,f4,f5,f6,f7,f8,
  f9,f10,f11,f12,f13,f14,f15] = fpregisters