[pypy-commit] pypy vecopt: picked lltype.cast changes for cast to bool, implemented int_is_true as a vector operation

plan_rich noreply at buildbot.pypy.org
Mon Jul 27 11:47:59 CEST 2015


Author: Richard Plangger <rich at pasra.at>
Branch: vecopt
Changeset: r78679:658ac4e3b571
Date: 2015-07-27 11:48 +0200
http://bitbucket.org/pypy/pypy/changeset/658ac4e3b571/

Log:	picked lltype.cast changes for cast to bool, implemented int_is_true
	as a vector operation

diff --git a/pypy/module/micronumpy/types.py b/pypy/module/micronumpy/types.py
--- a/pypy/module/micronumpy/types.py
+++ b/pypy/module/micronumpy/types.py
@@ -358,7 +358,8 @@
 
     @specialize.argtype(1)
     def box(self, value):
-        if value:
+        boolean = rffi.cast(self.T, value)
+        if boolean:
             return self._True
         else:
             return self._False
diff --git a/rpython/jit/backend/llsupport/assembler.py b/rpython/jit/backend/llsupport/assembler.py
--- a/rpython/jit/backend/llsupport/assembler.py
+++ b/rpython/jit/backend/llsupport/assembler.py
@@ -69,7 +69,7 @@
         self.rtyper = cpu.rtyper
         self._debug = False
 
-    def stitch_bridge(self, failargs, token):
+    def stitch_bridge(self, faildescr, token):
         raise NotImplementedError
 
     def setup_once(self):
diff --git a/rpython/jit/backend/x86/assembler.py b/rpython/jit/backend/x86/assembler.py
--- a/rpython/jit/backend/x86/assembler.py
+++ b/rpython/jit/backend/x86/assembler.py
@@ -589,7 +589,7 @@
                                                        rawstart, fullsize)
         return AsmInfo(ops_offset, startpos + rawstart, codeendpos - startpos)
 
-    def attach_bridge(self, faildescr, token):
+    def stitch_bridge(self, faildescr, token):
         rawstart = self.materialize_loop(token)
         self.patch_jump_for_descr(faildescr, rawstart)
 
diff --git a/rpython/jit/backend/x86/regloc.py b/rpython/jit/backend/x86/regloc.py
--- a/rpython/jit/backend/x86/regloc.py
+++ b/rpython/jit/backend/x86/regloc.py
@@ -609,7 +609,7 @@
 
         possible_instr_unrolled = unrolling_iterable([(1,'B_xx'),(2,'W_xx'),(4,'D_xx'),(8,'Q_xx')])
 
-        def INSN(self, size, loc1, loc2):
+        def INSN(self, loc1, loc2, size):
             code1 = loc1.location_code()
             code2 = loc2.location_code()
             assert code1 == code2 == 'x'
diff --git a/rpython/jit/backend/x86/vector_ext.py b/rpython/jit/backend/x86/vector_ext.py
--- a/rpython/jit/backend/x86/vector_ext.py
+++ b/rpython/jit/backend/x86/vector_ext.py
@@ -52,8 +52,11 @@
             # reset to zeros
             self.mc.PXOR(temp, temp)
 
-        self.mc.PCMPEQ(size, loc, temp)
+        # cmp with zeros (in temp) creates ones at each slot where it is zero
+        self.mc.PCMPEQ(loc, temp, size)
+        # temp converted to ones
         self.mc.PCMPEQQ(temp, temp)
+        # test if all slots are zero
         self.mc.PTEST(loc, temp)
 
     # vector operations
@@ -163,6 +166,21 @@
             elif itemsize == 8:
                 self.mc.MOVUPD(dest_loc, value_loc)
 
+    def genop_vec_int_is_true(self, op, arglocs, resloc):
+        loc, size = arglocs
+        temp = X86_64_XMM_SCRATCH_REG
+        self.mc.PXOR(temp, temp)
+        # every entry that is non zero -> becomes zero
+        # zero entries become ones
+        self.mc.PCMPEQ(loc, temp, size)
+        # a second time -> every zero entry (corresponding to non zero
+        # entries before) become ones
+        self.mc.PCMPEQ(loc, temp, size)
+
+    def genop_guard_vec_int_is_true(self, op, guard_op, guard_token, arglocs, resloc):
+        self._guard_vector_true(op, arglocs[0])
+        self.implement_guard(guard_token, 'NZ')
+
     def genop_vec_int_mul(self, op, arglocs, resloc):
         loc0, loc1, itemsize_loc = arglocs
         itemsize = itemsize_loc.value
@@ -605,6 +623,17 @@
         tosize = result.getsize()
         self.perform(op, [resloc, imm(size), imm(tosize)], resloc)
 
+    def consider_vec_int_is_true(self, op, guard_op):
+        args = op.getarglist()
+        resloc = self.xrm.force_result_in_reg(op.result, op.getarg(0), args)
+        sizearg = op.getarg(0)
+        assert isinstance(sizearg, BoxVector)
+        size = sizearg.getsize()
+        if guard_op is not None:
+            self.perform_with_guard(op, guard_op, [resloc,imm(size)], None)
+        else:
+            self.perform(op, [resloc,imm(size)], None)
+
     def consider_vec_box(self, op):
         # pseudo instruction, needed to create a new variable
         self.xrm.force_allocate_reg(op.result)
diff --git a/rpython/jit/codewriter/jtransform.py b/rpython/jit/codewriter/jtransform.py
--- a/rpython/jit/codewriter/jtransform.py
+++ b/rpython/jit/codewriter/jtransform.py
@@ -1273,7 +1273,9 @@
             return
 
         result = []
-        if min2:
+        if v_result.concretetype is lltype.Bool:
+            result.append(SpaceOperation('int_is_true', [v_arg], v_result))
+        elif min2:
             c_bytes = Constant(size2, lltype.Signed)
             result.append(SpaceOperation('int_signext', [v_arg, c_bytes],
                                          v_result))
diff --git a/rpython/jit/metainterp/optimizeopt/schedule.py b/rpython/jit/metainterp/optimizeopt/schedule.py
--- a/rpython/jit/metainterp/optimizeopt/schedule.py
+++ b/rpython/jit/metainterp/optimizeopt/schedule.py
@@ -750,6 +750,7 @@
     rop.VEC_FLOAT_ABS:   FLOAT_SINGLE_ARG_OP_TO_VOP,
     rop.VEC_FLOAT_NEG:   FLOAT_SINGLE_ARG_OP_TO_VOP,
     rop.VEC_FLOAT_EQ:    OpToVectorOp((PT_FLOAT_GENERIC,PT_FLOAT_GENERIC), INT_RES),
+    rop.VEC_INT_IS_TRUE: OpToVectorOp((PT_INT_GENERIC,PT_INT_GENERIC), PT_INT_GENERIC),
 
     rop.VEC_RAW_LOAD:         LOAD_TRANS,
     rop.VEC_GETARRAYITEM_RAW: LOAD_TRANS,
diff --git a/rpython/jit/metainterp/resoperation.py b/rpython/jit/metainterp/resoperation.py
--- a/rpython/jit/metainterp/resoperation.py
+++ b/rpython/jit/metainterp/resoperation.py
@@ -497,6 +497,7 @@
     'VEC_FLOAT_ABS/1',
     '_VEC_ARITHMETIC_LAST',
     'VEC_FLOAT_EQ/2',
+    'VEC_INT_IS_TRUE/1b',
 
     '_VEC_CAST_FIRST',
     'VEC_INT_SIGNEXT/2',
@@ -805,6 +806,7 @@
     rop.FLOAT_ABS: rop.VEC_FLOAT_ABS,
     rop.FLOAT_NEG: rop.VEC_FLOAT_NEG,
     rop.FLOAT_EQ:  rop.VEC_FLOAT_EQ,
+    rop.INT_IS_TRUE: rop.VEC_INT_IS_TRUE,
 
     # casts
     rop.INT_SIGNEXT: rop.VEC_INT_SIGNEXT,


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