[pypy-commit] pypy stmgc-c4: do a ptr_eq on guard_value() comparing two ptrs

[Raemi]

Author: Remi Meier <remi.meier at gmail.com>
Branch: stmgc-c4
Changeset: r66015:2ec55a5b3061
Date: 2013-08-07 10:35 +0200
http://bitbucket.org/pypy/pypy/changeset/2ec55a5b3061/

Log:	do a ptr_eq on guard_value() comparing two ptrs

diff --git a/rpython/jit/backend/llsupport/test/zrpy_gc_test.py b/rpython/jit/backend/llsupport/test/zrpy_gc_test.py
--- a/rpython/jit/backend/llsupport/test/zrpy_gc_test.py
+++ b/rpython/jit/backend/llsupport/test/zrpy_gc_test.py
@@ -829,6 +829,10 @@
             raiseassert(x0 is not None)
             raiseassert(x1 is not None)
             raiseassert(x3 is None)
+            for i in range(1, 4):
+                ptrs[i].x = i
+            x0.x = 6
+            x1.x = 9
             #
             return n - 1, x, x0, x1, x2, x3, x4, x5, x6, x7, ptrs, s
         return before, f, None
diff --git a/rpython/jit/backend/x86/assembler.py b/rpython/jit/backend/x86/assembler.py
--- a/rpython/jit/backend/x86/assembler.py
+++ b/rpython/jit/backend/x86/assembler.py
@@ -1613,7 +1613,12 @@
         # base_loc and ofs_loc should be immediates, but maybe not
         # fitting in 32-bit
         base_loc, ofs_loc, size_loc = arglocs
-        self.mc.INC(addr_add(base_loc, ofs_loc))
+        addr = addr_add(base_loc, ofs_loc)
+        if rx86.fits_in_32bits(addr.value):
+            self.mc.INC(addr)
+        else:
+            self.mc.MOV(X86_64_SCRATCH_REG, base_loc)
+            self.mc.INC_m((X86_64_SCRATCH_REG.value, ofs_loc.getint()))
 
     def genop_discard_setfield_gc(self, op, arglocs):
         base_loc, ofs_loc, size_loc, value_loc = arglocs
@@ -1798,7 +1803,15 @@
     genop_guard_guard_isnull = genop_guard_guard_false
 
     def genop_guard_guard_value(self, ign_1, guard_op, guard_token, locs, ign_2):
-        if guard_op.getarg(0).type == FLOAT:
+        argtype = guard_op.getarg(0).type
+        if self.cpu.gc_ll_descr.stm and argtype == REF:
+            assert guard_op.getarg(1).type == REF
+            # x64 has no support for 64bit immed. Force them into registers!
+            # XXX: do better for 32 bit
+            self.genop_guard_ptr_eq(ign_1, guard_op, guard_token, 
+                                    locs, ign_2)
+            return
+        elif argtype == FLOAT:
             assert guard_op.getarg(1).type == FLOAT
             self.mc.UCOMISD(locs[0], locs[1])
         else:
diff --git a/rpython/jit/backend/x86/regalloc.py b/rpython/jit/backend/x86/regalloc.py
--- a/rpython/jit/backend/x86/regalloc.py
+++ b/rpython/jit/backend/x86/regalloc.py
@@ -407,8 +407,16 @@
     consider_guard_overflow    = consider_guard_no_exception
 
     def consider_guard_value(self, op):
-        x = self.make_sure_var_in_reg(op.getarg(0))
-        y = self.loc(op.getarg(1))
+        args = op.getarglist()
+        if args[0].type == REF:
+            assert args[1].type == REF
+            # XXX: this is certainly not wanted.
+            # We force immed64 into registers here.
+            x = self.make_sure_var_in_reg(args[0], args, selected_reg=ecx)
+            y = self.make_sure_var_in_reg(args[1], args, selected_reg=eax)
+        else:
+            x = self.make_sure_var_in_reg(args[0], args)
+            y = self.loc(args[1])
         self.perform_guard(op, [x, y], None)
 
     def consider_guard_class(self, op):