[pypy-commit] pypy default: more register clobbering issues in _store_and_reset_exception

[bivab]

Author: David Schneider <david.schneider at picle.org>
Branch: 
Changeset: r63562:a801192368b9
Date: 2013-04-23 04:08 -0500
http://bitbucket.org/pypy/pypy/changeset/a801192368b9/

Log:	more register clobbering issues in _store_and_reset_exception

diff --git a/rpython/jit/backend/arm/assembler.py b/rpython/jit/backend/arm/assembler.py
--- a/rpython/jit/backend/arm/assembler.py
+++ b/rpython/jit/backend/arm/assembler.py
@@ -109,22 +109,25 @@
         assert excvalloc is not r.ip
         assert exctploc is not r.ip
         tmpreg = r.lr
+        mc.gen_load_int(r.ip.value, self.cpu.pos_exc_value())
         if excvalloc is not None: # store
             assert excvalloc.is_reg()
-            mc.gen_load_int(r.ip.value, self.cpu.pos_exc_value())
             self.load_reg(mc, excvalloc, r.ip)
         if on_frame:
             # store exc_value in JITFRAME
             ofs = self.cpu.get_ofs_of_frame_field('jf_guard_exc')
             assert check_imm_arg(ofs)
+            #
             self.load_reg(mc, r.ip, r.ip, helper=tmpreg)
+            #
             self.store_reg(mc, r.ip, r.fp, ofs, helper=tmpreg)
-            mc.gen_load_int(r.ip.value, self.cpu.pos_exc_value())
         if exctploc is not None:
             # store pos_exception in exctploc
             assert exctploc.is_reg()
-            mc.gen_load_int(tmpreg.value, self.cpu.pos_exception())
-            self.load_reg(mc, exctploc, tmpreg)
+            mc.gen_load_int(r.ip.value, self.cpu.pos_exception())
+            self.load_reg(mc, exctploc, r.ip, helper=tmpreg)
+
+        if on_frame or exctploc is not None:
             mc.gen_load_int(r.ip.value, self.cpu.pos_exc_value())
 
         # reset exception