[pypy-commit] pypy default: merge
fijal
noreply at buildbot.pypy.org
Fri Apr 19 17:03:55 CEST 2013
Author: Maciej Fijalkowski <fijall at gmail.com>
Branch:
Changeset: r63505:93e73352baa9
Date: 2013-04-19 17:03 +0200
http://bitbucket.org/pypy/pypy/changeset/93e73352baa9/
Log: merge
diff --git a/rpython/jit/backend/test/runner_test.py b/rpython/jit/backend/test/runner_test.py
--- a/rpython/jit/backend/test/runner_test.py
+++ b/rpython/jit/backend/test/runner_test.py
@@ -3935,3 +3935,19 @@
descr = self.cpu.get_latest_descr(frame)
assert descr.identifier == 42
assert not self.cpu.grab_exc_value(frame)
+
+ def test_setarrayitem_raw_short(self):
+ # setarrayitem_raw(140737353744432, 0, 30583, descr=<ArrayS 2>)
+ A = rffi.CArray(rffi.SHORT)
+ arraydescr = self.cpu.arraydescrof(A)
+ a = lltype.malloc(A, 2, flavor='raw')
+ a[0] = rffi.cast(rffi.SHORT, 666)
+ a[1] = rffi.cast(rffi.SHORT, 777)
+ a_int = rffi.cast(lltype.Signed, a)
+ print 'a_int:', a_int
+ self.execute_operation(rop.SETARRAYITEM_RAW,
+ [ConstInt(a_int), ConstInt(0), ConstInt(-7654)],
+ 'void', descr=arraydescr)
+ assert rffi.cast(lltype.Signed, a[0]) == -7654
+ assert rffi.cast(lltype.Signed, a[1]) == 777
+ lltype.free(a, flavor='raw')
diff --git a/rpython/jit/backend/x86/regloc.py b/rpython/jit/backend/x86/regloc.py
--- a/rpython/jit/backend/x86/regloc.py
+++ b/rpython/jit/backend/x86/regloc.py
@@ -521,17 +521,6 @@
return func_with_new_name(INSN, "INSN_" + name)
- def _16_bit_binaryop(name):
- def INSN(self, loc1, loc2):
- # Select 16-bit operand mode
- self.writechar('\x66')
- # XXX: Hack to let immediate() in rx86 know to do a 16-bit encoding
- self._use_16_bit_immediate = True
- getattr(self, name)(loc1, loc2)
- self._use_16_bit_immediate = False
-
- return INSN
-
def _addr_as_reg_offset(self, addr):
# Encodes a (64-bit) address as an offset from the scratch register.
# If we are within a "reuse_scratch_register" block, we remember the
@@ -616,10 +605,10 @@
NEG = _unaryop('NEG')
CMP = _binaryop('CMP')
- CMP16 = _16_bit_binaryop('CMP')
+ CMP16 = _binaryop('CMP16')
MOV = _binaryop('MOV')
MOV8 = _binaryop('MOV8')
- MOV16 = _16_bit_binaryop('MOV')
+ MOV16 = _binaryop('MOV16')
MOVZX8 = _binaryop('MOVZX8')
MOVSX8 = _binaryop('MOVSX8')
MOVZX16 = _binaryop('MOVZX16')
diff --git a/rpython/jit/backend/x86/rx86.py b/rpython/jit/backend/x86/rx86.py
--- a/rpython/jit/backend/x86/rx86.py
+++ b/rpython/jit/backend/x86/rx86.py
@@ -125,10 +125,7 @@
elif width == 'q' and mc.WORD == 8:
mc.writeimm64(immediate)
else:
- if mc._use_16_bit_immediate:
- mc.writeimm16(immediate)
- else:
- mc.writeimm32(immediate)
+ mc.writeimm32(immediate)
return 0
def immediate(argnum, width='i'):
@@ -282,16 +279,20 @@
# (the immediate address itself must be explicitely encoded as well,
# with immediate(argnum)).
-def encode_abs(mc, _1, _2, orbyte):
+ at specialize.arg(2)
+def encode_abs(mc, immediate, _, orbyte):
# expands to either '\x05' on 32-bit, or '\x04\x25' on 64-bit
if mc.WORD == 8:
mc.writechar(chr(0x04 | orbyte))
mc.writechar(chr(0x25))
else:
mc.writechar(chr(0x05 | orbyte))
+ # followed by an immediate, always 32 bits
+ mc.writeimm32(immediate)
return 0
-abs_ = encode_abs, 0, None, None
+def abs_(argnum):
+ return encode_abs, argnum, None, None
# ____________________________________________________________
# For 64-bits mode: the REX.W, REX.R, REX.X, REG.B prefixes
@@ -305,9 +306,6 @@
def encode_rex(mc, rexbyte, basevalue, orbyte):
if mc.WORD == 8:
assert 0 <= rexbyte < 8
- # XXX: Hack. Ignore REX.W if we are using 16-bit operands
- if mc._use_16_bit_immediate:
- basevalue &= ~REX_W
if basevalue != 0 or rexbyte != 0:
if basevalue == 0:
basevalue = 0x40
@@ -374,9 +372,8 @@
INSN_br = insn(rex_w, chr(base+1), register(2,8), stack_bp(1))
INSN_rb = insn(rex_w, chr(base+3), register(1,8), stack_bp(2))
INSN_rm = insn(rex_w, chr(base+3), register(1,8), mem_reg_plus_const(2))
- INSN_rj = insn(rex_w, chr(base+3), register(1,8), abs_, immediate(2))
- INSN_ji8 = insn(rex_w, '\x83', orbyte(base), abs_, immediate(1),
- immediate(2,'b'))
+ INSN_rj = insn(rex_w, chr(base+3), register(1,8), abs_(2))
+ INSN_ji8 = insn(rex_w, '\x83', orbyte(base), abs_(1), immediate(2,'b'))
INSN_mi8 = insn(rex_w, '\x83', orbyte(base), mem_reg_plus_const(1),
immediate(2,'b'))
INSN_bi8 = insn(rex_w, '\x83', orbyte(base), stack_bp(1), immediate(2,'b'))
@@ -449,9 +446,6 @@
class AbstractX86CodeBuilder(object):
"""Abstract base class."""
- # Used by the 16-bit version of instructions
- _use_16_bit_immediate = False
-
def writechar(self, char):
raise NotImplementedError
@@ -489,15 +483,13 @@
CMP_mi = select_8_or_32_bit_immed(CMP_mi8, CMP_mi32)
CMP_mr = insn(rex_w, '\x39', register(2, 8), mem_reg_plus_const(1))
- CMP_ji8 = insn(rex_w, '\x83', orbyte(7<<3), abs_,
- immediate(1), immediate(2, 'b'))
- CMP_ji32 = insn(rex_w, '\x81', orbyte(7<<3), abs_,
- immediate(1), immediate(2))
+ CMP_ji8 = insn(rex_w, '\x83', orbyte(7<<3), abs_(1), immediate(2, 'b'))
+ CMP_ji32 = insn(rex_w, '\x81', orbyte(7<<3), abs_(1), immediate(2))
CMP_ji = select_8_or_32_bit_immed(CMP_ji8, CMP_ji32)
- CMP_jr = insn(rex_w, '\x39', register(2, 8), abs_, immediate(1))
+ CMP_jr = insn(rex_w, '\x39', register(2, 8), abs_(1))
CMP32_mi = insn(rex_nw, '\x81', orbyte(7<<3), mem_reg_plus_const(1), immediate(2))
-
+ CMP16_mi = insn('\x66', rex_nw, '\x81', orbyte(7<<3), mem_reg_plus_const(1), immediate(2, 'h'))
CMP8_ri = insn(rex_fw, '\x80', byte_register(1), '\xF8', immediate(2, 'b'))
AND8_rr = insn(rex_fw, '\x20', byte_register(1), byte_register(2,8), '\xC0')
@@ -505,7 +497,7 @@
OR8_rr = insn(rex_fw, '\x08', byte_register(1), byte_register(2,8), '\xC0')
OR8_mi = insn(rex_nw, '\x80', orbyte(1<<3), mem_reg_plus_const(1),
immediate(2, 'b'))
- OR8_ji = insn(rex_nw, '\x80', orbyte(1<<3), abs_, immediate(1),
+ OR8_ji = insn(rex_nw, '\x80', orbyte(1<<3), abs_(1),
immediate(2, 'b'))
NEG_r = insn(rex_w, '\xF7', register(1), '\xD8')
@@ -556,7 +548,7 @@
LEA32_rb = insn(rex_w, '\x8D', register(1,8),stack_bp(2,force_32bits=True))
LEA_ra = insn(rex_w, '\x8D', register(1, 8), mem_reg_plus_scaled_reg_plus_const(2))
LEA_rm = insn(rex_w, '\x8D', register(1, 8), mem_reg_plus_const(2))
- LEA_rj = insn(rex_w, '\x8D', register(1, 8), abs_, immediate(2))
+ LEA_rj = insn(rex_w, '\x8D', register(1, 8), abs_(2))
CALL_l = insn('\xE8', relative(1))
CALL_r = insn(rex_nw, '\xFF', register(1), chr(0xC0 | (2<<3)))
@@ -583,11 +575,11 @@
TEST8_mi = insn(rex_nw, '\xF6', orbyte(0<<3), mem_reg_plus_const(1), immediate(2, 'b'))
TEST8_bi = insn(rex_nw, '\xF6', orbyte(0<<3), stack_bp(1), immediate(2, 'b'))
- TEST8_ji = insn(rex_nw, '\xF6', orbyte(0<<3), abs_, immediate(1), immediate(2, 'b'))
+ TEST8_ji = insn(rex_nw, '\xF6', orbyte(0<<3), abs_(1), immediate(2, 'b'))
TEST_rr = insn(rex_w, '\x85', register(2,8), register(1), '\xC0')
BTS_mr = insn(rex_w, '\x0F\xAB', register(2,8), mem_reg_plus_const(1))
- BTS_jr = insn(rex_w, '\x0F\xAB', register(2,8), abs_, immediate(1))
+ BTS_jr = insn(rex_w, '\x0F\xAB', register(2,8), abs_(1))
# x87 instructions
FSTPL_b = insn('\xDD', orbyte(3<<3), stack_bp(1)) # rffi.DOUBLE ('as' wants L??)
@@ -718,7 +710,7 @@
add_insn('s', stack_sp(modrm_argnum))
add_insn('m', mem_reg_plus_const(modrm_argnum))
add_insn('a', mem_reg_plus_scaled_reg_plus_const(modrm_argnum))
- add_insn('j', abs_, immediate(modrm_argnum))
+ add_insn('j', abs_(modrm_argnum))
# Define a regular MOV, and a variant MOV32 that only uses the low 4 bytes of a
# register
@@ -729,6 +721,8 @@
define_modrm_modes('MOV8_*r', [rex_fw, '\x88', byte_register(2, 8)], regtype='BYTE')
define_modrm_modes('MOV8_*i', [rex_fw, '\xC6', orbyte(0<<3)], [immediate(2, 'b')], regtype='BYTE')
+define_modrm_modes('MOV16_*r', ['\x66', rex_nw, '\x89', register(2, 8)])
+define_modrm_modes('MOV16_*i', ['\x66', rex_nw, '\xC7', orbyte(0<<3)], [immediate(2, 'h')])
define_modrm_modes('MOVZX8_r*', [rex_w, '\x0F\xB6', register(1, 8)], regtype='BYTE')
define_modrm_modes('MOVSX8_r*', [rex_w, '\x0F\xBE', register(1, 8)], regtype='BYTE')
@@ -766,7 +760,7 @@
#
assert insnname_template.count('*') == 1
add_insn('x', register(2), '\xC0')
- add_insn('j', abs_, immediate(2))
+ add_insn('j', abs_(2))
add_insn('m', mem_reg_plus_const(2))
define_pxmm_insn('PADDQ_x*', '\xD4')
diff --git a/rpython/memory/gc/minimark.py b/rpython/memory/gc/minimark.py
--- a/rpython/memory/gc/minimark.py
+++ b/rpython/memory/gc/minimark.py
@@ -130,6 +130,7 @@
FORWARDSTUB = lltype.GcStruct('forwarding_stub',
('forw', llmemory.Address))
FORWARDSTUBPTR = lltype.Ptr(FORWARDSTUB)
+NURSARRAY = lltype.Array(llmemory.Address)
# ____________________________________________________________
@@ -263,7 +264,7 @@
self.nursery_top = NULL
self.nursery_real_top = NULL
self.debug_tiny_nursery = -1
- self.debug_rotating_nurseries = None
+ self.debug_rotating_nurseries = lltype.nullptr(NURSARRAY)
self.extra_threshold = 0
#
# The ArenaCollection() handles the nonmovable objects allocation.
@@ -471,23 +472,32 @@
# and use them alternatively, while mprotect()ing the unused
# ones to detect invalid access.
debug_start("gc-debug")
- self.debug_rotating_nurseries = []
- for i in range(22):
+ self.debug_rotating_nurseries = lltype.malloc(
+ NURSARRAY, 22, flavor='raw', track_allocation=False)
+ i = 0
+ while i < 22:
nurs = self._alloc_nursery()
llarena.arena_protect(nurs, self._nursery_memory_size(), True)
- self.debug_rotating_nurseries.append(nurs)
+ self.debug_rotating_nurseries[i] = nurs
+ i += 1
debug_print("allocated", len(self.debug_rotating_nurseries),
"extra nurseries")
debug_stop("gc-debug")
def debug_rotate_nursery(self):
- if self.debug_rotating_nurseries is not None:
+ if self.debug_rotating_nurseries:
debug_start("gc-debug")
oldnurs = self.nursery
llarena.arena_protect(oldnurs, self._nursery_memory_size(), True)
- self.debug_rotating_nurseries.append(oldnurs)
#
- newnurs = self.debug_rotating_nurseries.pop(0)
+ newnurs = self.debug_rotating_nurseries[0]
+ i = 0
+ while i < len(self.debug_rotating_nurseries) - 1:
+ self.debug_rotating_nurseries[i] = (
+ self.debug_rotating_nurseries[i + 1])
+ i += 1
+ self.debug_rotating_nurseries[i] = oldnurs
+ #
llarena.arena_protect(newnurs, self._nursery_memory_size(), False)
self.nursery = newnurs
self.nursery_top = self.nursery + self.initial_cleanup
diff --git a/rpython/memory/gctransform/framework.py b/rpython/memory/gctransform/framework.py
--- a/rpython/memory/gctransform/framework.py
+++ b/rpython/memory/gctransform/framework.py
@@ -619,6 +619,12 @@
func = getattr(graph, 'func', None)
if func and getattr(func, '_gc_no_collect_', False):
if self.collect_analyzer.analyze_direct_call(graph):
+ print '!'*79
+ ca = CollectAnalyzer(self.translator)
+ ca.verbose = True
+ ca.analyze_direct_call(graph)
+ # ^^^ for the dump of which operation in which graph actually
+ # causes it to return True
raise Exception("'no_collect' function can trigger collection:"
" %s" % func)
diff --git a/rpython/translator/backendopt/graphanalyze.py b/rpython/translator/backendopt/graphanalyze.py
--- a/rpython/translator/backendopt/graphanalyze.py
+++ b/rpython/translator/backendopt/graphanalyze.py
@@ -80,21 +80,21 @@
if graph is None:
x = self.analyze_external_call(op, seen)
if self.verbose and x:
- print '\tanalyze_external_call %s: %r' % (op, x)
+ self.dump_info('analyze_external_call %s: %r' % (op, x))
return x
x = self.analyze_direct_call(graph, seen)
if self.verbose and x:
- print '\tanalyze_direct_call(%s): %r' % (graph, x)
+ self.dump_info('analyze_direct_call(%s): %r' % (graph, x))
return x
elif op.opname == "indirect_call":
graphs = op.args[-1].value
if graphs is None:
if self.verbose:
- print '\t%s to unknown' % (op,)
+ self.dump_info('%s to unknown' % (op,))
return self.top_result()
x = self.analyze_indirect_call(graphs, seen)
if self.verbose and x:
- print '\tanalyze_indirect_call(%s): %r' % (graphs, x)
+ self.dump_info('analyze_indirect_call(%s): %r' % (graphs, x))
return x
elif op.opname == "oosend":
name = op.args[0].value
@@ -106,9 +106,12 @@
return self.analyze_oosend(TYPE, name, seen)
x = self.analyze_simple_operation(op, graphinfo)
if self.verbose and x:
- print '\t%s: %r' % (op, x)
+ self.dump_info('%s: %r' % (op, x))
return x
+ def dump_info(self, info):
+ print '[%s] %s' % (self.__class__.__name__, info)
+
def analyze_direct_call(self, graph, seen=None):
if seen is None:
seen = DependencyTracker(self)
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