[pypy-commit] pypy arm-backend-2: implement int_force_ge_zero for ARM
bivab
noreply at buildbot.pypy.org
Tue Aug 7 09:15:58 CEST 2012
Author: David Schneider <david.schneider at picle.org>
Branch: arm-backend-2
Changeset: r56616:8849756a4cf1
Date: 2012-08-06 13:25 +0000
http://bitbucket.org/pypy/pypy/changeset/8849756a4cf1/
Log: implement int_force_ge_zero for ARM
diff --git a/pypy/jit/backend/arm/opassembler.py b/pypy/jit/backend/arm/opassembler.py
--- a/pypy/jit/backend/arm/opassembler.py
+++ b/pypy/jit/backend/arm/opassembler.py
@@ -94,6 +94,12 @@
self.mc.MUL(res.value, reg1.value, reg2.value)
return fcond
+ def emit_op_int_force_ge_zero(self, op, arglocs, regalloc, fcond):
+ arg, res = arglocs
+ self.mc.CMP_ri(arg.value, 0)
+ self.mc.MOV_ri(res.value, 0, cond=c.LT)
+ self.mc.MOV_rr(res.value, arg.value, cond=c.GE)
+
#ref: http://blogs.arm.com/software-enablement/detecting-overflow-from-mul/
def emit_guard_int_mul_ovf(self, op, guard, arglocs, regalloc, fcond):
reg1 = arglocs[0]
diff --git a/pypy/jit/backend/arm/regalloc.py b/pypy/jit/backend/arm/regalloc.py
--- a/pypy/jit/backend/arm/regalloc.py
+++ b/pypy/jit/backend/arm/regalloc.py
@@ -497,6 +497,11 @@
res = self.force_allocate_reg(op.result)
self.possibly_free_var(op.result)
return [reg1, reg2, res]
+
+ def prepare_op_int_force_ge_zero(self, op, fcond):
+ argloc = self._ensure_value_is_boxed(op.getarg(0))
+ resloc = self.force_allocate_reg(op.result, [op.getarg(0)])
+ return [argloc, resloc]
def prepare_guard_int_mul_ovf(self, op, guard, fcond):
boxes = op.getarglist()
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