[pypy-commit] pypy default: Swap the operands of CMOVNS to match the Intel order used everywhere else
arigo
noreply at buildbot.pypy.org
Mon Aug 6 15:43:07 CEST 2012
Author: Armin Rigo <arigo at tunes.org>
Branch:
Changeset: r56605:404802d7596f
Date: 2012-08-06 15:42 +0200
http://bitbucket.org/pypy/pypy/changeset/404802d7596f/
Log: Swap the operands of CMOVNS to match the Intel order used everywhere
else in the backend. Remove the skip in test_rx86_32_auto_encoding.
diff --git a/pypy/jit/backend/x86/assembler.py b/pypy/jit/backend/x86/assembler.py
--- a/pypy/jit/backend/x86/assembler.py
+++ b/pypy/jit/backend/x86/assembler.py
@@ -1396,7 +1396,7 @@
def genop_int_force_ge_zero(self, op, arglocs, resloc):
self.mc.TEST(arglocs[0], arglocs[0])
self.mov(imm0, resloc)
- self.mc.CMOVNS(arglocs[0], resloc)
+ self.mc.CMOVNS(resloc, arglocs[0])
def genop_int_mod(self, op, arglocs, resloc):
if IS_X86_32:
diff --git a/pypy/jit/backend/x86/rx86.py b/pypy/jit/backend/x86/rx86.py
--- a/pypy/jit/backend/x86/rx86.py
+++ b/pypy/jit/backend/x86/rx86.py
@@ -530,7 +530,7 @@
NOT_r = insn(rex_w, '\xF7', register(1), '\xD0')
NOT_b = insn(rex_w, '\xF7', orbyte(2<<3), stack_bp(1))
- CMOVNS_rr = insn(rex_w, '\x0F\x49', register(2, 8), register(1), '\xC0')
+ CMOVNS_rr = insn(rex_w, '\x0F\x49', register(1, 8), register(2), '\xC0')
# ------------------------------ Misc stuff ------------------------------
diff --git a/pypy/jit/backend/x86/test/test_rx86_32_auto_encoding.py b/pypy/jit/backend/x86/test/test_rx86_32_auto_encoding.py
--- a/pypy/jit/backend/x86/test/test_rx86_32_auto_encoding.py
+++ b/pypy/jit/backend/x86/test/test_rx86_32_auto_encoding.py
@@ -317,9 +317,7 @@
# CALL_j is actually relative, so tricky to test
(instrname == 'CALL' and argmodes == 'j') or
# SET_ir must be tested manually
- (instrname == 'SET' and argmodes == 'ir') or
- # asm gets CMOVNS args the wrong way
- (instrname.startswith('CMOV'))
+ (instrname == 'SET' and argmodes == 'ir')
)
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