[pypy-commit] pypy arm-backend-2: combine all the mixins for operation implementations and change the assembler setup
bivab
noreply at buildbot.pypy.org
Thu Apr 5 14:19:02 CEST 2012
Author: David Schneider <david.schneider at picle.org>
Branch: arm-backend-2
Changeset: r54197:3f8b478d181b
Date: 2012-03-27 12:21 +0000
http://bitbucket.org/pypy/pypy/changeset/3f8b478d181b/
Log: combine all the mixins for operation implementations and change the
assembler setup
diff --git a/pypy/jit/backend/arm/assembler.py b/pypy/jit/backend/arm/assembler.py
--- a/pypy/jit/backend/arm/assembler.py
+++ b/pypy/jit/backend/arm/assembler.py
@@ -14,6 +14,7 @@
from pypy.jit.backend.llsupport.asmmemmgr import MachineDataBlockWrapper
from pypy.jit.backend.model import CompiledLoopToken
from pypy.jit.codewriter import longlong
+from pypy.jit.codewriter.effectinfo import EffectInfo
from pypy.jit.metainterp.history import AbstractFailDescr, INT, REF, FLOAT
from pypy.jit.metainterp.history import BoxInt, ConstInt
from pypy.jit.metainterp.resoperation import rop, ResOperation
@@ -1264,24 +1265,25 @@
asm_operations = [notimplemented_op] * (rop._LAST + 1)
asm_operations_with_guard = [notimplemented_op_with_guard] * (rop._LAST + 1)
+asm_math_operations = {}
-for key, value in rop.__dict__.items():
- key = key.lower()
- if key.startswith('_'):
- continue
- methname = 'emit_op_%s' % key
- if hasattr(AssemblerARM, methname):
- func = getattr(AssemblerARM, methname).im_func
- asm_operations[value] = func
-
-for key, value in rop.__dict__.items():
- key = key.lower()
- if key.startswith('_'):
- continue
- methname = 'emit_guard_%s' % key
- if hasattr(AssemblerARM, methname):
- func = getattr(AssemblerARM, methname).im_func
- asm_operations_with_guard[value] = func
+for name, value in ResOpAssembler.__dict__.iteritems():
+ if name.startswith('emit_guard_'):
+ opname = name[len('emit_guard_'):]
+ num = getattr(rop, opname.upper())
+ asm_operations_with_guard[num] = value
+ elif name.startswith('emit_op_llong_'):
+ opname = name[len('emit_op_llong_'):]
+ num = getattr(EffectInfo, 'OS_LLONG_' + opname.upper())
+ asm_llong_operations[num] = value
+ elif name.startswith('emit_op_math_'):
+ opname = name[len('emit_op_math_'):]
+ num = getattr(EffectInfo, 'OS_MATH_' + opname.upper())
+ asm_math_operations[num] = value
+ elif name.startswith('emit_op_'):
+ opname = name[len('emit_op_'):]
+ num = getattr(rop, opname.upper())
+ asm_operations[num] = value
class BridgeAlreadyCompiled(Exception):
diff --git a/pypy/jit/backend/arm/opassembler.py b/pypy/jit/backend/arm/opassembler.py
--- a/pypy/jit/backend/arm/opassembler.py
+++ b/pypy/jit/backend/arm/opassembler.py
@@ -45,9 +45,7 @@
self.fcond = fcond
-class IntOpAsslember(object):
-
- _mixin_ = True
+class ResOpAssembler(object):
def emit_op_int_add(self, op, arglocs, regalloc, fcond, flags=False):
l0, l1, res = arglocs
@@ -162,10 +160,6 @@
emit_op_int_sub_ovf = emit_op_int_sub
-class UnaryIntOpAssembler(object):
-
- _mixin_ = True
-
emit_op_int_is_true = gen_emit_op_unary_cmp('int_is_true', c.NE)
emit_op_int_is_zero = gen_emit_op_unary_cmp('int_is_zero', c.EQ)
@@ -184,10 +178,6 @@
return fcond
-class GuardOpAssembler(object):
-
- _mixin_ = True
-
def _emit_guard(self, op, arglocs, fcond, save_exc,
is_guard_not_invalidated=False):
assert isinstance(save_exc, bool)
@@ -291,10 +281,6 @@
is_guard_not_invalidated=True)
-class OpAssembler(object):
-
- _mixin_ = True
-
def emit_op_jump(self, op, arglocs, regalloc, fcond):
# The backend's logic assumes that the target code is in a piece of
# assembler that was also called with the same number of arguments,
@@ -616,10 +602,6 @@
emit_op_cond_call_gc_wb_array = emit_op_cond_call_gc_wb
-class FieldOpAssembler(object):
-
- _mixin_ = True
-
def emit_op_setfield_gc(self, op, arglocs, regalloc, fcond):
value_loc, base_loc, ofs, size = arglocs
if size.value == 8:
@@ -760,10 +742,6 @@
emit_op_setinteriorfield_raw = emit_op_setinteriorfield_gc
-class ArrayOpAssember(object):
-
- _mixin_ = True
-
def emit_op_arraylen_gc(self, op, arglocs, regalloc, fcond):
res, base_loc, ofs = arglocs
self.mc.LDR_ri(res.value, base_loc.value, ofs.value)
@@ -846,10 +824,6 @@
emit_op_getarrayitem_gc_pure = emit_op_getarrayitem_gc
-class StrOpAssembler(object):
-
- _mixin_ = True
-
def emit_op_strlen(self, op, arglocs, regalloc, fcond):
l0, l1, res = arglocs
if l1.is_imm():
@@ -998,11 +972,7 @@
raise AssertionError("bad unicode item size")
-class UnicodeOpAssembler(object):
-
- _mixin_ = True
-
- emit_op_unicodelen = StrOpAssembler.emit_op_strlen
+ emit_op_unicodelen = emit_op_strlen
def emit_op_unicodegetitem(self, op, arglocs, regalloc, fcond):
res, base_loc, ofs_loc, scale, basesize, itemsize = arglocs
@@ -1032,10 +1002,6 @@
return fcond
-class ForceOpAssembler(object):
-
- _mixin_ = True
-
def emit_op_force_token(self, op, arglocs, regalloc, fcond):
res_loc = arglocs[0]
self.mc.MOV_rr(res_loc.value, r.fp.value)
@@ -1248,10 +1214,6 @@
self.mc.STR_ri(r.ip.value, r.fp.value)
-class AllocOpAssembler(object):
-
- _mixin_ = True
-
def emit_op_call_malloc_gc(self, op, arglocs, regalloc, fcond):
self.emit_op_call(op, arglocs, regalloc, fcond)
self.propagate_memoryerror_if_r0_is_null()
@@ -1282,9 +1244,6 @@
self.mc.NOP()
-class FloatOpAssemlber(object):
- _mixin_ = True
-
emit_op_float_add = gen_emit_float_op('float_add', 'VADD')
emit_op_float_sub = gen_emit_float_op('float_sub', 'VSUB')
emit_op_float_mul = gen_emit_float_op('float_mul', 'VMUL')
@@ -1324,10 +1283,3 @@
return fcond
-class ResOpAssembler(GuardOpAssembler, IntOpAsslember,
- OpAssembler, UnaryIntOpAssembler,
- FieldOpAssembler, ArrayOpAssember,
- StrOpAssembler, UnicodeOpAssembler,
- ForceOpAssembler, AllocOpAssembler,
- FloatOpAssemlber):
- pass
diff --git a/pypy/jit/backend/arm/regalloc.py b/pypy/jit/backend/arm/regalloc.py
--- a/pypy/jit/backend/arm/regalloc.py
+++ b/pypy/jit/backend/arm/regalloc.py
@@ -543,7 +543,7 @@
oopspecindex = effectinfo.oopspecindex
if oopspecindex == EffectInfo.OS_MATH_SQRT:
args = self.prepare_op_math_sqrt(op, fcond)
- self.assembler.emit_op_math_sqrt(op, args, self, fcond)
+ self.perform_math(op, args, fcond)
return
return self._prepare_call(op)
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