[pypy-commit] pypy ppc-jit-backend: Implemented INT_FLOORDIV.

[hager]

Author: hager <sven.hager at uni-duesseldorf.de>
Branch: ppc-jit-backend
Changeset: r48198:14fd9b6e54bb
Date: 2011-10-17 20:16 +0200
http://bitbucket.org/pypy/pypy/changeset/14fd9b6e54bb/

Log:	Implemented INT_FLOORDIV.

diff --git a/pypy/jit/backend/ppc/ppcgen/opassembler.py b/pypy/jit/backend/ppc/ppcgen/opassembler.py
--- a/pypy/jit/backend/ppc/ppcgen/opassembler.py
+++ b/pypy/jit/backend/ppc/ppcgen/opassembler.py
@@ -45,6 +45,17 @@
         reg1, reg2, res = arglocs
         self.mc.mullw(res.value, reg1.value, reg2.value)
 
+    def emit_int_floordiv(self, op, arglocs, regalloc):
+        l0, l1, res = arglocs
+        if l0.is_imm():
+            self.mc.load_imm(r.r0, l0.value)
+            self.mc.divw(res.value, r.r0.value, l1.value)
+        elif l1.is_imm():
+            self.mc.load_imm(r.r0, l1.value)
+            self.mc.divw(res.value, l0.value, r.r0.value)
+        else:
+            self.mc.divw(res.value, l0.value, l1.value)
+
     emit_int_le = gen_emit_cmp_op(c.LE)   
 
     def _emit_guard(self, op, arglocs, fcond, save_exc=False,
diff --git a/pypy/jit/backend/ppc/ppcgen/regalloc.py b/pypy/jit/backend/ppc/ppcgen/regalloc.py
--- a/pypy/jit/backend/ppc/ppcgen/regalloc.py
+++ b/pypy/jit/backend/ppc/ppcgen/regalloc.py
@@ -5,7 +5,8 @@
 from pypy.jit.backend.ppc.ppcgen.jump import remap_frame_layout_mixed
 from pypy.jit.backend.ppc.ppcgen.locations import imm
 from pypy.jit.backend.ppc.ppcgen.helper.regalloc import (_check_imm_arg, 
-                                                         prepare_cmp_op)
+                                                         prepare_cmp_op,
+                                                         prepare_op_by_helper_call)
 from pypy.jit.metainterp.history import (INT, REF, FLOAT, Const, ConstInt, 
                                          ConstPtr, LoopToken)
 from pypy.jit.metainterp.resoperation import rop
@@ -221,6 +222,29 @@
         res = self.force_allocate_reg(op.result)
         return locs + [res]
 
+    def prepare_int_floordiv(self, op):
+        boxes = list(op.getarglist())
+        b0, b1 = boxes
+        imm_b0 = _check_imm_arg(b0)
+        imm_b1 = _check_imm_arg(b1)
+        if not imm_b0 and imm_b1:
+            l0, box = self._ensure_value_is_boxed(b0, boxes)
+            l1 = self.make_sure_var_in_reg(b1, [b0])
+            boxes.append(box)
+        elif imm_b0 and not imm_b1:
+            l0 = self.make_sure_var_in_reg(b0)
+            l1, box = self._ensure_value_is_boxed(b1, boxes)
+            boxes.append(box)
+        else:
+            l0, box = self._ensure_value_is_boxed(b0, boxes)
+            boxes.append(box)
+            l1, box = self._ensure_value_is_boxed(b1, boxes)
+            boxes.append(box)
+        locs = [l0, l1]
+        self.possibly_free_vars(boxes)
+        res = self.force_allocate_reg(op.result)
+        return locs + [res]
+
     def prepare_int_mul(self, op):
         boxes = list(op.getarglist())
         b0, b1 = boxes