[pypy-svn] pypy arm-backed-float: correct loading of constants when entering the loop and add more of the regalloc interface to the common regalloc for both kinds of registers

bivab commits-noreply at bitbucket.org
Wed Mar 30 17:31:32 CEST 2011


Author: David Schneider <david.schneider at picle.org>
Branch: arm-backed-float
Changeset: r43019:e252cb6eb4e2
Date: 2011-03-30 14:35 +0200
http://bitbucket.org/pypy/pypy/changeset/e252cb6eb4e2/

Log:	correct loading of constants when entering the loop and add more of
	the regalloc interface to the common regalloc for both kinds of
	registers

diff --git a/pypy/jit/backend/arm/assembler.py b/pypy/jit/backend/arm/assembler.py
--- a/pypy/jit/backend/arm/assembler.py
+++ b/pypy/jit/backend/arm/assembler.py
@@ -283,10 +283,10 @@
                     j += 1
                 elif arg.type == REF:
                     mem[j] = self.REF_TYPE
-					j += 1
+                    j += 1
                 elif arg.type == FLOAT:
                     mem[j] = self.FLOAT_TYPE
-					j += 1
+                    j += 1
                 else:
                     assert 0, 'unknown type'
 
@@ -341,18 +341,21 @@
         for i in range(len(inputargs)):
             loc = inputargs[i]
             reg = regalloc.force_allocate_reg(loc)
-            if loc.type == REF:
-                addr = self.fail_boxes_ptr.get_addr_for_num(i)
-            elif loc.type == INT:
-                addr = self.fail_boxes_int.get_addr_for_num(i)
+            if loc.type != FLOAT:
+                if loc.type == REF:
+                    addr = self.fail_boxes_ptr.get_addr_for_num(i)
+                elif loc.type == INT:
+                    addr = self.fail_boxes_int.get_addr_for_num(i)
+                else:
+                    assert 0
+                self.mc.gen_load_int(reg.value, addr)
+                self.mc.LDR_ri(reg.value, reg.value)
             elif loc.type == FLOAT:
                 addr = self.fail_boxes_float.get_addr_for_num(i)
+                self.mc.gen_load_int(r.ip.value, addr)
+                self.mc.VLDR(reg.value, r.ip.value)
             else:
-            self.mc.gen_load_int(r.ip.value, addr)
-            if not loc.type == FLOAT:
-                self.mc.LDR_ri(reg.value, r.ip.value)
-            else:
-                self.mc.VLDR(reg.value, r.ip.value)
+                assert 0
             regalloc.possibly_free_var(loc)
         arglocs = [regalloc.loc(arg) for arg in inputargs]
         looptoken._arm_arglocs = arglocs
@@ -396,7 +399,7 @@
         self._dump(operations)
         self.setup()
         longevity = compute_vars_longevity(inputargs, operations)
-        regalloc = ARMRegisterManager(longevity, assembler=self, frame_manager=ARMFrameManager())
+        regalloc = Regalloc(longevity, assembler=self, frame_manager=ARMFrameManager())
 
         clt = CompiledLoopToken(self.cpu, looptoken.number)
         looptoken.compiled_loop_token = clt
@@ -526,9 +529,9 @@
 
     def _walk_operations(self, operations, regalloc):
         fcond=c.AL
-        while regalloc.position < len(operations) - 1:
+        while regalloc.position() < len(operations) - 1:
             regalloc.next_instruction()
-            i = regalloc.position
+            i = regalloc.position()
             op = operations[i]
             opnum = op.getopnum()
             if op.has_no_side_effect() and op.result not in regalloc.longevity:

diff --git a/pypy/jit/backend/arm/opassembler.py b/pypy/jit/backend/arm/opassembler.py
--- a/pypy/jit/backend/arm/opassembler.py
+++ b/pypy/jit/backend/arm/opassembler.py
@@ -15,7 +15,7 @@
                                                     gen_emit_unary_float_op)
 from pypy.jit.backend.arm.codebuilder import ARMv7Builder, OverwritingBuilder
 from pypy.jit.backend.arm.jump import remap_frame_layout
-from pypy.jit.backend.arm.regalloc import Regalloc
+from pypy.jit.backend.arm.regalloc import Regalloc, TempInt
 from pypy.jit.backend.llsupport import symbolic
 from pypy.jit.backend.llsupport.descr import BaseFieldDescr, BaseArrayDescr
 from pypy.jit.backend.llsupport.regalloc import compute_vars_longevity, TempBox
@@ -654,7 +654,7 @@
         descr = op.getdescr()
         assert isinstance(descr, LoopToken)
         assert op.numargs() == len(descr._arm_arglocs)
-        resbox = TempBox()
+        resbox = TempInt()
         self._emit_call(descr._arm_direct_bootstrap_code, op.getarglist(),
                                 regalloc, fcond, result=resbox)
         if op.result is None:

diff --git a/pypy/jit/backend/arm/test/test_regalloc.py b/pypy/jit/backend/arm/test/test_regalloc.py
--- a/pypy/jit/backend/arm/test/test_regalloc.py
+++ b/pypy/jit/backend/arm/test/test_regalloc.py
@@ -8,7 +8,7 @@
 from pypy.jit.metainterp.resoperation import rop, ResOperation
 from pypy.jit.backend.llsupport.descr import GcCache
 from pypy.jit.backend.detect_cpu import getcpuclass
-from pypy.jit.backend.arm.regalloc import ARMRegisterManager
+from pypy.jit.backend.arm.regalloc import RegAlloc
 from pypy.jit.tool.oparser import parse
 from pypy.rpython.lltypesystem import lltype, llmemory, rffi
 from pypy.rpython.annlowlevel import llhelper
@@ -57,7 +57,7 @@
     def load_effective_addr(self, *args):
         self.lea.append(args)
 
-class RegAllocForTests(ARMRegisterManager):
+class RegAllocForTests(RegAlloc):
     position = 0
     def _compute_next_usage(self, v, _):
         return -1

diff --git a/pypy/jit/backend/arm/test/test_gc_integration.py b/pypy/jit/backend/arm/test/test_gc_integration.py
--- a/pypy/jit/backend/arm/test/test_gc_integration.py
+++ b/pypy/jit/backend/arm/test/test_gc_integration.py
@@ -10,7 +10,7 @@
 from pypy.jit.backend.llsupport.descr import GcCache
 from pypy.jit.backend.llsupport.gc import GcLLDescription
 from pypy.jit.backend.detect_cpu import getcpuclass
-from pypy.jit.backend.arm.regalloc import ARMRegisterManager
+from pypy.jit.backend.arm.regalloc import Regalloc
 from pypy.jit.backend.arm.arch import WORD
 from pypy.jit.tool.oparser import parse
 from pypy.rpython.lltypesystem import lltype, llmemory, rffi

diff --git a/pypy/jit/backend/arm/regalloc.py b/pypy/jit/backend/arm/regalloc.py
--- a/pypy/jit/backend/arm/regalloc.py
+++ b/pypy/jit/backend/arm/regalloc.py
@@ -112,6 +112,29 @@
             return self.vfprm.loc(var)
         else:
             return self.rm.loc(var)
+    
+    def position(self):
+        return self.rm.position
+
+    def next_instruction(self):
+        self.rm.next_instruction()
+        self.vfprm.next_instruction()
+
+    def _check_invariants(self):
+        self.rm._check_invariants()
+        self.vfprm._check_invariants()
+
+    def stays_alive(self, v):
+        if v.type == FLOAT:
+            return self.vfprm.stays_alive(v)
+        else:
+            return self.rm.stays_alive(v)
+
+    def after_call(self, v):
+        if v.type == FLOAT:
+            return self.vfprm.after_call(v)
+        else:
+            return self.rm.after_call(v)
 
     def force_allocate_reg(self, var, forbidden_vars=[], selected_reg=None,
                            need_lower_byte=False):
@@ -121,6 +144,12 @@
         else:
             return self.rm.force_allocate_reg(var, forbidden_vars,
                                               selected_reg, need_lower_byte)
+    def try_allocate_reg(self, v, selected_reg=None, need_lower_byte=False):
+        if v.type == FLOAT:
+            return self.vfprm.try_allocate_reg(v, selected_reg, need_lower_byte)
+        else:
+            return self.rm.try_allocate_reg(v, selected_reg, need_lower_byte)
+
     def possibly_free_var(self, var):
         if var.type == FLOAT:
             self.vfprm.possibly_free_var(var)


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