[pypy-svn] pypy arm-backed-float: correctly associate float registers when updating the bindings to compile a bridge
bivab
commits-noreply at bitbucket.org
Mon Apr 4 13:31:55 CEST 2011
Author: David Schneider <david.schneider at picle.org>
Branch: arm-backed-float
Changeset: r43138:fa8ce72df7c9
Date: 2011-04-02 14:58 +0200
http://bitbucket.org/pypy/pypy/changeset/fa8ce72df7c9/
Log: correctly associate float registers when updating the bindings to
compile a bridge
diff --git a/pypy/jit/backend/arm/helper/regalloc.py b/pypy/jit/backend/arm/helper/regalloc.py
--- a/pypy/jit/backend/arm/helper/regalloc.py
+++ b/pypy/jit/backend/arm/helper/regalloc.py
@@ -59,15 +59,13 @@
if base:
loc2, box2 = self._ensure_value_is_boxed(op.getarg(1))
locs.append(loc2)
- self.vfprm.possibly_free_var(box2)
- self.vfprm.possibly_free_var(box1)
+ self.possibly_free_var(box2)
+ self.possibly_free_var(box1)
if float_result:
res = self.vfprm.force_allocate_reg(op.result)
- self.vfprm.possibly_free_var(op.result)
else:
res = self.rm.force_allocate_reg(op.result)
- self.rm.possibly_free_var(op.result)
- self.vfprm.possibly_free_var(box1)
+ self.possibly_free_var(op.result)
locs.append(res)
return locs
return f
diff --git a/pypy/jit/backend/arm/regalloc.py b/pypy/jit/backend/arm/regalloc.py
--- a/pypy/jit/backend/arm/regalloc.py
+++ b/pypy/jit/backend/arm/regalloc.py
@@ -207,12 +207,11 @@
arg = inputargs[i]
i += 1
if loc.is_reg():
- if arg.type == FLOAT:
- self.vfprm.reg_bindings[arg] = loc
- else:
- self.rm.reg_bindings[arg] = loc
- #XXX add float
+ self.rm.reg_bindings[arg] = loc
+ elif loc.is_vfp_reg:
+ self.vfprm.reg_bindings[arg] = loc
else:
+ assert loc.is_stack()
self.frame_manager.frame_bindings[arg] = loc
used[loc] = None
More information about the Pypy-commit
mailing list