[pypy-svn] r78523 - pypy/branch/arm-backend/pypy/jit/backend/arm
david at codespeak.net
david at codespeak.net
Sat Oct 30 13:54:56 CEST 2010
Author: david
Date: Sat Oct 30 13:54:54 2010
New Revision: 78523
Modified:
pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py
pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py
pypy/branch/arm-backend/pypy/jit/backend/arm/instructions.py
pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py
Log:
Implement int_and, int_or, int_xor operations
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py Sat Oct 30 13:54:54 2010
@@ -169,7 +169,7 @@
# cpu interface
def assemble_loop(self, inputargs, operations, looptoken):
longevity = compute_vars_longevity(inputargs, operations)
- regalloc = ARMRegisterManager(longevity, assembler=self.mc, frame_manager=ARMFrameManager())
+ regalloc = ARMRegisterManager(longevity, assembler=self, frame_manager=ARMFrameManager())
self.align()
loop_start=self.mc.curraddr()
self.gen_func_prolog()
@@ -190,7 +190,7 @@
def assemble_bridge(self, faildescr, inputargs, operations):
enc = rffi.cast(rffi.CCHARP, faildescr._failure_recovery_code)
longevity = compute_vars_longevity(inputargs, operations)
- regalloc = ARMRegisterManager(longevity, assembler=self.mc, frame_manager=ARMFrameManager())
+ regalloc = ARMRegisterManager(longevity, assembler=self, frame_manager=ARMFrameManager())
regalloc.update_bindings(enc, inputargs)
bridge_head = self.mc.curraddr()
@@ -218,6 +218,13 @@
b.gen_load_int(reg.value, bridge_addr, fcond)
b.MOV_rr(r.pc.value, reg.value, cond=fcond)
+ # regalloc support
+ def regalloc_mov(self, prev_loc, loc):
+ if isinstance(prev_loc, ConstInt):
+ # XXX check size of imm for current instr
+ self.mc.gen_load_int(loc.value, prev_loc.getint())
+ else:
+ self.mc.MOV_rr(loc.value, prev_loc.value)
def make_operation_list():
def notimplemented(self, op, regalloc, fcond):
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py Sat Oct 30 13:54:54 2010
@@ -104,13 +104,6 @@
self.MOV_ri(ip, t, cond=cond)
self.ORR_rr(r, r, ip, offset, cond=cond)
- # regalloc support
- def regalloc_mov(self, prev_loc, loc):
- if isinstance(prev_loc, ConstInt):
- # XXX check size of imm for current instr
- self.gen_load_int(loc.value, prev_loc.getint())
- else:
- self.MOV_rr(loc.value, prev_loc.value)
class ARMv7InMemoryBuilder(AbstractARMv7Builder):
def __init__(self, start, end):
@@ -121,7 +114,7 @@
class ARMv7Builder(AbstractARMv7Builder):
def __init__(self):
- map_size = 1024
+ map_size = 4096
data = alloc(map_size)
self._pos = 0
self._init(data, map_size)
@@ -140,13 +133,13 @@
def _add_more_mem(self):
new_mem = alloc(self._size)
new_mem_addr = rffi.cast(lltype.Signed, new_mem)
- self.PUSH([reg.r0.value])
+ self.PUSH([reg.r0.value, reg.ip.value])
self.gen_load_int(reg.r0.value, new_mem_addr)
self.MOV_rr(reg.pc.value, reg.r0.value)
self._dump_trace('data%d.asm' % self.n_data)
self.n_data+=1
self._data = new_mem
self._pos = 0
- self.LDM(reg.sp.value, [reg.r0.value], w=1) # XXX Replace with POP instr. someday
+ self.LDM(reg.sp.value, [reg.r0.value, reg.ip.value], w=1) # XXX Replace with POP instr. someday
define_instructions(AbstractARMv7Builder)
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/instructions.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/instructions.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/instructions.py Sat Oct 30 13:54:54 2010
@@ -34,7 +34,7 @@
}
data_proc_imm = {
- 'ADD_ri': {'op': 0, 'rncond':'', 'result':True, 'base':True},
+ 'AND_ri': {'op': 0, 'rncond':'', 'result':True, 'base':True},
'EOR_ri': {'op': 0x2, 'rncond':'', 'result':True, 'base':True},
'SUB_ri': {'op': 0x4, 'rncond':'!0xF', 'result':True, 'base':True},
#'ADR_ri': {'op': 0x4, 'rncond':'0xF', 'result':True, 'base':True},
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py Sat Oct 30 13:54:54 2010
@@ -12,6 +12,35 @@
from pypy.rpython.annlowlevel import llhelper
from pypy.rpython.lltypesystem import lltype, rffi, llmemory
+def gen_emit_op_ri(opname):
+ def f(self, op, regalloc, fcond):
+ ri_op = getattr(self.mc, '%s_ri' % opname)
+ rr_op = getattr(self.mc, '%s_rr' % opname)
+
+ arg0 = op.getarg(0)
+ arg1 = op.getarg(1)
+ res = regalloc.try_allocate_reg(op.result)
+ if self._check_imm_arg(arg0, 0xFF) and not isinstance(arg1, ConstInt):
+ print 'arg0 is imm'
+ reg = regalloc.try_allocate_reg(arg1)
+ ri_op(res.value, reg.value, imm=arg0.getint(), cond=fcond)
+ elif self._check_imm_arg(arg1, 0xFF) and not isinstance(arg0, ConstInt):
+ print 'arg1 is imm'
+ box = Box()
+ reg = regalloc.try_allocate_reg(arg0)
+ ri_op(res.value, reg.value, imm=arg1.getint(), cond=fcond)
+ else:
+ print 'generating rr'
+ reg = self._put_in_reg(arg0, regalloc)
+ reg2 = self._put_in_reg(arg1, regalloc)
+ rr_op(res.value, reg.value, reg2.value)
+ regalloc.possibly_free_var(reg2)
+
+ regalloc.possibly_free_var(res)
+ regalloc.possibly_free_var(reg)
+ return fcond
+ return f
+
class IntOpAsslember(object):
_mixin_ = True
@@ -89,11 +118,11 @@
return fcond
def emit_op_int_mod(self, op, regalloc, fcond):
+ res = regalloc.force_allocate_reg(op.result)
arg1 = regalloc.make_sure_var_in_reg(op.getarg(0), selected_reg=r.r0)
arg2 = regalloc.make_sure_var_in_reg(op.getarg(1), selected_reg=r.r1)
assert arg1 == r.r0
assert arg2 == r.r1
- res = regalloc.try_allocate_reg(op.result)
self.mc.MOD(fcond)
self.mc.MOV_rr(res.value, r.r0.value, cond=fcond)
regalloc.possibly_free_vars_for_op(op)
@@ -108,6 +137,14 @@
reg = regalloc.try_allocate_reg(box)
return reg
+ emit_op_int_and = gen_emit_op_ri('AND')
+ emit_op_int_or = gen_emit_op_ri('ORR')
+ emit_op_int_xor = gen_emit_op_ri('EOR')
+
+ def _check_imm_arg(self, arg, size):
+ return isinstance(arg, ConstInt) and arg.getint() <= size and arg.getint() >= 0
+
+
class GuardOpAssembler(object):
_mixin_ = True
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