[pypy-svn] r78284 - in pypy/branch/arm-backend/pypy/jit/backend/arm: . test
david at codespeak.net
david at codespeak.net
Tue Oct 26 11:36:43 CEST 2010
Author: david
Date: Tue Oct 26 11:36:42 2010
New Revision: 78284
Modified:
pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py
pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py
pypy/branch/arm-backend/pypy/jit/backend/arm/regalloc.py
pypy/branch/arm-backend/pypy/jit/backend/arm/registers.py
pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_assembler.py
pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py
Log:
Introduce locations for registers and replace register numbers with the locations
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py Tue Oct 26 11:36:42 2010
@@ -80,16 +80,16 @@
functype = lltype.Ptr(lltype.FuncType([lltype.Signed, lltype.Signed], lltype.Signed))
decode_registers_addr = llhelper(functype, self.failure_recovery_func)
self.mc.PUSH(range(12)) # registers r0 .. r11
- self.mc.MOV_rr(r.r0, r.lr) # move mem block address, to r0 to pass as
+ self.mc.MOV_rr(r.r0.value, r.lr.value) # move mem block address, to r0 to pass as
# parameter to next procedure call
- self.mc.MOV_rr(r.r1, r.sp) # pass the current stack pointer as second param
- self.mc.gen_load_int(r.r2, rffi.cast(lltype.Signed, decode_registers_addr))
- self.mc.gen_load_int(r.lr, self.mc.curraddr()+self.mc.size_of_gen_load_int+WORD)
- self.mc.MOV_rr(r.pc, r.r2)
- self.mc.MOV_rr(r.ip, r.r0)
- self.mc.LDM(r.sp, range(12), w=1) # XXX Replace with POP instr. someday
+ self.mc.MOV_rr(r.r1.value, r.sp.value) # pass the current stack pointer as second param
+ self.mc.gen_load_int(r.r2.value, rffi.cast(lltype.Signed, decode_registers_addr))
+ self.mc.gen_load_int(r.lr.value, self.mc.curraddr()+self.mc.size_of_gen_load_int+WORD)
+ self.mc.MOV_rr(r.pc.value, r.r2.value)
+ self.mc.MOV_rr(r.ip.value, r.r0.value)
+ self.mc.LDM(r.sp.value, range(12), w=1) # XXX Replace with POP instr. someday
- self.mc.MOV_rr(r.r0, r.ip)
+ self.mc.MOV_rr(r.r0.value, r.ip.value)
self.gen_func_epilog()
@@ -101,7 +101,7 @@
for i in range(len(args)):
if args[i]:
curreg = regalloc.try_allocate_reg(args[i])
- mem[i] = chr(curreg)
+ mem[i] = chr(curreg.value)
else:
mem[i] = '\xFE'
@@ -112,11 +112,14 @@
n = self.cpu.get_fail_descr_number(op.getdescr())
self.encode32(mem, i+1, n)
- self.mc.gen_load_int(r.lr, memaddr, cond=fcond)
- self.mc.gen_load_int(reg, self.mc.baseaddr(), cond=fcond)
- self.mc.MOV_rr(r.pc, reg, cond=fcond)
-
- op.getdescr()._arm_guard_reg = reg
+ self.mc.gen_load_int(r.lr.value, memaddr, cond=fcond)
+ self.mc.gen_load_int(reg.value, self.mc.baseaddr(), cond=fcond)
+ self.mc.MOV_rr(r.pc.value, reg.value, cond=fcond)
+
+ # This register is used for patching when assembling a bridge
+ # guards going to be patched are allways conditional
+ if fcond != c.AL:
+ op.getdescr()._arm_guard_reg = reg
return memaddr
def align(self):
@@ -124,18 +127,18 @@
self.mc.writechar(chr(0))
def gen_func_epilog(self,cond=c.AL):
- self.mc.LDM(r.sp, r.callee_restored_registers, cond=cond, w=1)
+ self.mc.LDM(r.sp.value, [reg.value for reg in r.callee_restored_registers], cond=cond, w=1)
def gen_func_prolog(self):
- self.mc.PUSH(r.callee_saved_registers)
+ self.mc.PUSH([reg.value for reg in r.callee_saved_registers])
def gen_bootstrap_code(self, inputargs, regalloc, looptoken):
regs = []
for i in range(len(inputargs)):
reg = regalloc.try_allocate_reg(inputargs[i])
addr = self.fail_boxes_int.get_addr_for_num(i)
- self.mc.gen_load_int(reg, addr)
- self.mc.LDR_ri(reg, reg)
+ self.mc.gen_load_int(reg.value, addr)
+ self.mc.LDR_ri(reg.value, reg.value)
regs.append(reg)
looptoken._arm_arglocs = regs
@@ -187,8 +190,8 @@
fcond = faildescr._arm_guard_cond
b = ARMv7InMemoryBuilder(faildescr._arm_guard_code, faildescr._arm_guard_code+100)
reg = faildescr._arm_guard_reg
- b.gen_load_int(reg, bridge_addr, fcond)
- b.MOV_rr(r.pc, reg, cond=fcond)
+ b.gen_load_int(reg.value, bridge_addr, fcond)
+ b.MOV_rr(r.pc.value, reg.value, cond=fcond)
# Resoperations
@@ -200,10 +203,10 @@
reg = regalloc.try_allocate_reg(op.getarg(i))
inpreg = registers[i]
# XXX only if every value is in a register
- self.mc.MOV_rr(inpreg, reg)
+ self.mc.MOV_rr(inpreg.value, reg.value)
loop_code = op.getdescr()._arm_loop_code
- self.mc.gen_load_int(tmpreg, loop_code)
- self.mc.MOV_rr(r.pc, tmpreg)
+ self.mc.gen_load_int(tmpreg.value, loop_code)
+ self.mc.MOV_rr(r.pc.value, tmpreg.value)
regalloc.possibly_free_var(tmpreg)
return fcond
@@ -214,14 +217,14 @@
def emit_op_int_le(self, op, regalloc, fcond):
reg = regalloc.try_allocate_reg(op.getarg(0))
assert isinstance(op.getarg(1), ConstInt)
- self.mc.CMP(reg, op.getarg(1).getint())
+ self.mc.CMP(reg.value, op.getarg(1).getint())
return c.GT
def emit_op_int_add(self, op, regalloc, fcond):
reg = regalloc.try_allocate_reg(op.getarg(0))
res = regalloc.try_allocate_reg(op.result)
assert isinstance(op.getarg(1), ConstInt)
- self.mc.ADD_ri(res, reg, op.getarg(1).getint())
+ self.mc.ADD_ri(res.value, reg.value, op.getarg(1).getint())
regalloc.possibly_free_vars_for_op(op)
return fcond
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py Tue Oct 26 11:36:42 2010
@@ -70,15 +70,18 @@
size_of_gen_load_int = 7 * WORD
def gen_load_int(self, r, value, cond=cond.AL):
- assert r != reg.ip, 'ip is used to load int'
+ """r is the register number, value is the value to be loaded to the
+ register"""
+ assert r != reg.ip.value, 'ip is used to load int'
self.MOV_ri(r, (value & 0xFF), cond=cond)
+ ip = reg.ip.value
for offset in range(8, 25, 8):
t = (value >> offset) & 0xFF
#if t == 0:
# continue
- self.MOV_ri(reg.ip, t, cond=cond)
- self.ORR_rr(r, r, reg.ip, offset, cond=cond)
+ self.MOV_ri(ip, t, cond=cond)
+ self.ORR_rr(r, r, ip, offset, cond=cond)
class ARMv7InMemoryBuilder(AbstractARMv7Builder):
def __init__(self, start, end):
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/regalloc.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/regalloc.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/regalloc.py Tue Oct 26 11:36:42 2010
@@ -5,7 +5,7 @@
class ARMRegisterManager(RegisterManager):
all_regs = r.all_regs
box_types = None # or a list of acceptable types
- no_lower_byte_regs = r.all_regs
+ no_lower_byte_regs = all_regs
save_around_call_regs = all_regs
def __init__(self, longevity, frame_manager=None, assembler=None):
@@ -16,7 +16,7 @@
for i in range(len(inputargs)):
while enc[j] == '\xFE':
j += 1
- self.try_allocate_reg(inputargs[i], ord(enc[j]))
+ self.try_allocate_reg(inputargs[i], r.all_regs[ord(enc[j])])
j += 1
class ARMFrameManager(FrameManager):
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/registers.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/registers.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/registers.py Tue Oct 26 11:36:42 2010
@@ -1,12 +1,17 @@
-r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15 = range(16)
+from pypy.jit.backend.arm.locations import RegisterLocation
+
+registers = [RegisterLocation(i) for i in range(16)]
+r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15 = registers
+
# aliases for registers
-fp = 11
-ip = 12
-sp = 13
-lr = 14
-pc = 15
+fp = r11
+ip = r12
+sp = r13
+lr = r14
+pc = r15
+
+all_regs = registers[:12]
-all_regs = range(12)
callee_resp = [r4, r5, r6, r7, r8, r9, r10, r11]
callee_saved_registers = callee_resp+[lr]
callee_restored_registers = callee_resp+[pc]
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_assembler.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_assembler.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_assembler.py Tue Oct 26 11:36:42 2010
@@ -21,78 +21,78 @@
def test_load_small_int_to_reg(self):
self.a.gen_func_prolog()
- self.a.mc.gen_load_int(r.r0, 123)
+ self.a.mc.gen_load_int(r.r0.value, 123)
self.a.gen_func_epilog()
assert run_asm(self.a) == 123
def test_load_medium_int_to_reg(self):
self.a.gen_func_prolog()
- self.a.mc.gen_load_int(r.r0, 0xBBD7)
+ self.a.mc.gen_load_int(r.r0.value, 0xBBD7)
self.a.gen_func_epilog()
assert run_asm(self.a) == 48087
def test_load_int_to_reg(self):
self.a.gen_func_prolog()
- self.a.mc.gen_load_int(r.r0, 0xFFFFFF85)
+ self.a.mc.gen_load_int(r.r0.value, 0xFFFFFF85)
self.a.gen_func_epilog()
assert run_asm(self.a) == -123
def test_or(self):
self.a.gen_func_prolog()
- self.a.mc.MOV_ri(r.r1, 8)
- self.a.mc.MOV_ri(r.r2, 8)
- self.a.mc.ORR_rr(r.r0, r.r1, r.r2, 4)
+ self.a.mc.MOV_ri(r.r1.value, 8)
+ self.a.mc.MOV_ri(r.r2.value, 8)
+ self.a.mc.ORR_rr(r.r0.value, r.r1.value, r.r2.value, 4)
self.a.gen_func_epilog()
assert run_asm(self.a) == 0x88
def test_sub(self):
self.a.gen_func_prolog()
- self.a.mc.gen_load_int(r.r1, 123456)
- self.a.mc.SUB_ri(r.r0, r.r1, 123)
+ self.a.mc.gen_load_int(r.r1.value, 123456)
+ self.a.mc.SUB_ri(r.r0.value, r.r1.value, 123)
self.a.gen_func_epilog()
assert run_asm(self.a) == 123333
def test_cmp(self):
self.a.gen_func_prolog()
- self.a.mc.gen_load_int(r.r1, 22)
- self.a.mc.CMP(r.r1, 123)
- self.a.mc.MOV_ri(r.r0, 1, c.LE)
- self.a.mc.MOV_ri(r.r0, 0, c.GT)
+ self.a.mc.gen_load_int(r.r1.value, 22)
+ self.a.mc.CMP(r.r1.value, 123)
+ self.a.mc.MOV_ri(r.r0.value, 1, c.LE)
+ self.a.mc.MOV_ri(r.r0.value, 0, c.GT)
self.a.gen_func_epilog()
assert run_asm(self.a) == 1
def test_int_le_false(self):
self.a.gen_func_prolog()
- self.a.mc.gen_load_int(r.r1, 2222)
- self.a.mc.CMP(r.r1, 123)
- self.a.mc.MOV_ri(r.r0, 1, c.LE)
- self.a.mc.MOV_ri(r.r0, 0, c.GT)
+ self.a.mc.gen_load_int(r.r1.value, 2222)
+ self.a.mc.CMP(r.r1.value, 123)
+ self.a.mc.MOV_ri(r.r0.value, 1, c.LE)
+ self.a.mc.MOV_ri(r.r0.value, 0, c.GT)
self.a.gen_func_epilog()
assert run_asm(self.a) == 0
def test_simple_jump(self):
self.a.gen_func_prolog()
- self.a.mc.MOV_ri(r.r1, 1)
+ self.a.mc.MOV_ri(r.r1.value, 1)
loop_head = self.a.mc.curraddr()
- self.a.mc.CMP(r.r1, 0) # z=0, z=1
- self.a.mc.MOV_ri(r.r1, 0, cond=c.NE)
- self.a.mc.MOV_ri(r.r1, 7, cond=c.EQ)
- self.a.mc.gen_load_int(r.r4, loop_head, cond=c.NE)
- self.a.mc.MOV_rr(r.pc, r.r4, cond=c.NE)
- self.a.mc.MOV_rr(r.r0, r.r1)
+ self.a.mc.CMP(r.r1.value, 0) # z=0, z=1
+ self.a.mc.MOV_ri(r.r1.value, 0, cond=c.NE)
+ self.a.mc.MOV_ri(r.r1.value, 7, cond=c.EQ)
+ self.a.mc.gen_load_int(r.r4.value, loop_head, cond=c.NE)
+ self.a.mc.MOV_rr(r.pc.value, r.r4.value, cond=c.NE)
+ self.a.mc.MOV_rr(r.r0.value, r.r1.value)
self.a.gen_func_epilog()
assert run_asm(self.a) == 7
def test_jump(self):
self.a.gen_func_prolog()
- self.a.mc.MOV_ri(r.r1, 1)
+ self.a.mc.MOV_ri(r.r1.value, 1)
loop_head = self.a.mc.curraddr()
- self.a.mc.ADD_ri(r.r1, r.r1, 1)
- self.a.mc.CMP(r.r1, 9)
- self.a.mc.gen_load_int(r.r4, loop_head, cond=c.NE)
- self.a.mc.MOV_rr(r.pc, r.r4, cond=c.NE)
- self.a.mc.MOV_rr(r.r0, r.r1)
+ self.a.mc.ADD_ri(r.r1.value, r.r1.value, 1)
+ self.a.mc.CMP(r.r1.value, 9)
+ self.a.mc.gen_load_int(r.r4.value, loop_head, cond=c.NE)
+ self.a.mc.MOV_rr(r.pc.value, r.r4.value, cond=c.NE)
+ self.a.mc.MOV_rr(r.r0.value, r.r1.value)
self.a.gen_func_epilog()
assert run_asm(self.a) == 9
@@ -101,10 +101,10 @@
functype = lltype.Ptr(lltype.FuncType([lltype.Signed], lltype.Signed))
call_addr = rffi.cast(lltype.Signed, llhelper(functype, callme))
self.a.gen_func_prolog()
- self.a.mc.MOV_ri(r.r0, 123)
- self.a.mc.gen_load_int(r.r1, call_addr)
- self.a.mc.gen_load_int(r.lr, self.a.mc.curraddr()+self.a.mc.size_of_gen_load_int+WORD)
- self.a.mc.MOV_rr(r.pc, r.r1)
+ self.a.mc.MOV_ri(r.r0.value, 123)
+ self.a.mc.gen_load_int(r.r1.value, call_addr)
+ self.a.mc.gen_load_int(r.lr.value, self.a.mc.curraddr()+self.a.mc.size_of_gen_load_int+WORD)
+ self.a.mc.MOV_rr(r.pc.value, r.r1.value)
self.a.gen_func_epilog()
assert run_asm(self.a) == 133
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_instr_codebuilder.py Tue Oct 26 11:36:42 2010
@@ -25,97 +25,97 @@
self.cb = CodeBuilder()
def test_ldr(self):
- self.cb.LDR_ri(r.r0, r.r1)
+ self.cb.LDR_ri(r.r0.value, r.r1.value)
self.assert_equal('LDR r0, [r1]')
def test_ldr_neg(self):
- self.cb.LDR_ri(r.r3, r.fp, -16)
+ self.cb.LDR_ri(r.r3.value, r.fp.value, -16)
self.assert_equal('LDR r3, [fp, #-16]')
def test_add_ri(self):
- self.cb.ADD_ri(r.r0, r.r1, 1)
+ self.cb.ADD_ri(r.r0.value, r.r1.value, 1)
self.assert_equal('ADD r0, r1, #1')
def test_mov_rr(self):
- self.cb.MOV_rr(r.r7, r.r12)
+ self.cb.MOV_rr(r.r7.value, r.r12.value)
self.assert_equal('MOV r7, r12')
def test_mov_ri(self):
- self.cb.MOV_ri(r.r9, 123)
+ self.cb.MOV_ri(r.r9.value, 123)
self.assert_equal('MOV r9, #123')
def test_mov_ri2(self):
- self.cb.MOV_ri(r.r9, 255)
+ self.cb.MOV_ri(r.r9.value, 255)
self.assert_equal('MOV r9, #255')
def test_mov_ri_max(self):
py.test.skip('Check the actual largest thing')
- self.cb.MOV_ri(r.r9, 0xFFF)
+ self.cb.MOV_ri(r.r9.value, 0xFFF)
self.assert_equal('MOV r9, #4095')
def test_str_ri(self):
- self.cb.STR_ri(r.r9, r.r14)
+ self.cb.STR_ri(r.r9.value, r.r14.value)
self.assert_equal('STR r9, [r14]')
def test_str_ri_offset(self):
- self.cb.STR_ri(r.r9, r.r14, 23)
+ self.cb.STR_ri(r.r9.value, r.r14.value, 23)
self.assert_equal('STR r9, [r14, #23]')
def test_str_ri_offset(self):
- self.cb.STR_ri(r.r9, r.r14, -20)
+ self.cb.STR_ri(r.r9.value, r.r14.value, -20)
self.assert_equal('STR r9, [r14, #-20]')
def test_asr_ri(self):
- self.cb.ASR_ri(r.r7, r.r5, 24)
+ self.cb.ASR_ri(r.r7.value, r.r5.value, 24)
self.assert_equal('ASR r7, r5, #24')
def test_orr_rr_no_shift(self):
- self.cb.ORR_rr(r.r0, r.r7,r.r12)
+ self.cb.ORR_rr(r.r0.value, r.r7.value,r.r12.value)
self.assert_equal('ORR r0, r7, r12')
def test_orr_rr_lsl_8(self):
- self.cb.ORR_rr(r.r0, r.r7,r.r12, 8)
+ self.cb.ORR_rr(r.r0.value, r.r7.value,r.r12.value, 8)
self.assert_equal('ORR r0, r7, r12, lsl #8')
def test_push_one_reg(self):
- self.cb.PUSH([r.r1])
+ self.cb.PUSH([r.r1.value])
self.assert_equal('PUSH {r1}')
def test_push_multiple(self):
- self.cb.PUSH([r.r1, r.r3, r.r6, r.r8, r.pc])
+ self.cb.PUSH([reg.value for reg in [r.r1, r.r3, r.r6, r.r8, r.pc]])
self.assert_equal('PUSH {r1, r3, r6, r8, pc}')
def test_push_multiple2(self):
- self.cb.PUSH([r.fp, r.ip, r.lr, r.pc])
+ self.cb.PUSH([reg.value for reg in [r.fp, r.ip, r.lr, r.pc]])
self.assert_equal('PUSH {fp, ip, lr, pc}')
def test_ldm_one_reg(self):
- self.cb.LDM(r.sp, [r.fp])
+ self.cb.LDM(r.sp.value, [r.fp.value])
self.assert_equal('LDM sp, {fp}')
def test_ldm_multiple_reg(self):
- self.cb.LDM(r.sp, [r.fp, r.ip, r.lr])
+ self.cb.LDM(r.sp.value, [reg.value for reg in [r.fp, r.ip, r.lr]])
self.assert_equal('LDM sp, {fp, ip, lr}')
def test_ldm_multiple_reg2(self):
- self.cb.LDM(r.sp, [r.fp, r.sp, r.pc])
+ self.cb.LDM(r.sp.value, [reg.value for reg in [r.fp, r.sp, r.pc]])
self.assert_equal("LDM sp, {fp, sp, pc}")
def test_sub_ri(self):
- self.cb.SUB_ri(r.r2, r.r4, 123)
+ self.cb.SUB_ri(r.r2.value, r.r4.value, 123)
self.assert_equal('SUB r2, r4, #123')
def test_sub_ri2(self):
py.test.skip('XXX check the actual largest value')
- self.cb.SUB_ri(r.r3, r.r7, 0xFFF)
+ self.cb.SUB_ri(r.r3.value, r.r7.value, 0xFFF)
self.assert_equal('SUB r3, r7, #4095')
def test_cmp_ri(self):
- self.cb.CMP(r.r3, 123)
+ self.cb.CMP(r.r3.value, 123)
self.assert_equal('CMP r3, #123')
def test_mcr(self):
- self.cb.MCR(15, 0, r.r1, 7, 10,0)
+ self.cb.MCR(15, 0, r.r1.value, 7, 10,0)
self.assert_equal('MCR P15, 0, r1, c7, c10, 0')
@@ -149,31 +149,31 @@
if table['result'] and table['base']:
def f(self):
func = getattr(self.cb, name)
- func(r.r3, r.r7, 23)
+ func(r.r3.value, r.r7.value, 23)
self.assert_equal('%s r3, r7, #23' % name[:name.index('_')])
elif not table['base']:
def f(self):
func = getattr(self.cb, name)
- func(r.r3, 23)
+ func(r.r3.value, 23)
self.assert_equal('%s r3, #23' % name[:name.index('_')])
else:
def f(self):
func = getattr(self.cb, name)
- func(r.r3, 23)
+ func(r.r3.value, 23)
self.assert_equal('%s r3, #23' % name[:name.index('_')])
return f
def gen_test_imm_func(name, table):
def f(self):
func = getattr(self.cb, name)
- func(r.r3, r.r7, 23)
+ func(r.r3.value, r.r7.value, 23)
self.assert_equal('%s r3, [r7, #23]' % name[:name.index('_')])
return f
def gen_test_reg_func(name, table):
def f(self):
func = getattr(self.cb, name)
- func(r.r3, r.r7, r.r12)
+ func(r.r3.value, r.r7.value, r.r12.value)
self.assert_equal('%s r3, [r7, r12]' % name[:name.index('_')])
return f
@@ -181,18 +181,18 @@
if name[-2:] == 'ri':
def f(self):
func = getattr(self.cb, name)
- func(r.r3, r.r7, 12)
+ func(r.r3.value, r.r7.value, 12)
self.assert_equal('%s r3, r7, #12' % name[:name.index('_')])
elif table['base'] and table['result']:
def f(self):
func = getattr(self.cb, name)
- func(r.r3, r.r7, r.r12)
+ func(r.r3.value, r.r7.value, r.r12.value)
self.assert_equal('%s r3, r7, r12' % name[:name.index('_')])
else:
def f(self):
func = getattr(self.cb, name)
- func(r.r3, r.r7)
+ func(r.r3.value, r.r7.value)
self.assert_equal('%s r3, r7' % name[:name.index('_')])
return f
More information about the Pypy-commit
mailing list