[pypy-svn] r79513 - in pypy/branch/arm-backend/pypy/jit/backend/arm: . helper
david at codespeak.net
david at codespeak.net
Thu Nov 25 14:16:41 CET 2010
Author: david
Date: Thu Nov 25 14:16:40 2010
New Revision: 79513
Modified:
pypy/branch/arm-backend/pypy/jit/backend/arm/helper/assembler.py
pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py
Log:
Some register allocation fixes
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/helper/assembler.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/helper/assembler.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/helper/assembler.py Thu Nov 25 14:16:40 2010
@@ -27,17 +27,17 @@
imm_a0 = self._check_imm_arg(arg0, imm_size, allow_zero=allow_zero)
imm_a1 = self._check_imm_arg(arg1, imm_size, allow_zero=allow_zero)
if commutative and imm_a0:
- l0 = regalloc.make_sure_var_in_reg(arg0, imm_fine=imm_a0)
+ l0 = regalloc.make_sure_var_in_reg(arg0, [arg1], imm_fine=imm_a0)
l1 = regalloc.make_sure_var_in_reg(arg1, [arg0])
res = regalloc.force_allocate_reg(op.result, [arg0, arg1])
ri_op(res.value, l1.value, imm=l0.getint(), cond=fcond)
elif imm_a1:
- l0 = regalloc.make_sure_var_in_reg(arg0, imm_fine=False)
+ l0 = regalloc.make_sure_var_in_reg(arg0, [arg1], imm_fine=False)
l1 = regalloc.make_sure_var_in_reg(arg1, [arg0], imm_fine=True)
res = regalloc.force_allocate_reg(op.result, [arg0, arg1])
ri_op(res.value, l0.value, imm=l1.getint(), cond=fcond)
else:
- l0 = regalloc.make_sure_var_in_reg(arg0, imm_fine=False)
+ l0 = regalloc.make_sure_var_in_reg(arg0, [arg1], imm_fine=False)
l1 = regalloc.make_sure_var_in_reg(arg1, [arg0], imm_fine=False)
res = regalloc.force_allocate_reg(op.result, [arg0, arg1])
rr_op(res.value, l0.value, l1.value)
@@ -50,8 +50,8 @@
assert fcond is not None
a0 = op.getarg(0)
a1 = op.getarg(1)
- arg1 = regalloc.make_sure_var_in_reg(a0, [a1], selected_reg=r.r0, imm_fine=False)
- arg2 = regalloc.make_sure_var_in_reg(a1, [a0], selected_reg=r.r1, imm_fine=False)
+ arg1 = regalloc.make_sure_var_in_reg(a0, selected_reg=r.r0, imm_fine=False)
+ arg2 = regalloc.make_sure_var_in_reg(a1, selected_reg=r.r1, imm_fine=False)
assert arg1 == r.r0
assert arg2 == r.r1
regalloc.before_call()
@@ -78,13 +78,13 @@
imm_a0 = self._check_imm_arg(arg0)
imm_a1 = self._check_imm_arg(arg1)
if imm_a1 and not imm_a0:
- l0 = regalloc.make_sure_var_in_reg(arg0, imm_fine=False)
- l1 = regalloc.make_sure_var_in_reg(arg1, [l0])
+ l0 = regalloc.make_sure_var_in_reg(arg0, [arg1], imm_fine=False)
+ l1 = regalloc.make_sure_var_in_reg(arg1, [arg0])
res = regalloc.force_allocate_reg(op.result)
self.mc.CMP_ri(l0.value, imm=l1.getint(), cond=fcond)
else:
- l0 = regalloc.make_sure_var_in_reg(arg0, imm_fine=False)
- l1 = regalloc.make_sure_var_in_reg(arg1, [l0], imm_fine=False)
+ l0 = regalloc.make_sure_var_in_reg(arg0, [arg1], imm_fine=False)
+ l1 = regalloc.make_sure_var_in_reg(arg1, [arg0], imm_fine=False)
res = regalloc.force_allocate_reg(op.result)
self.mc.CMP_rr(l0.value, l1.value, cond=fcond)
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py Thu Nov 25 14:16:40 2010
@@ -49,9 +49,10 @@
l1 = regalloc.make_sure_var_in_reg(a1, forbidden_vars=[a0], imm_fine=False)
res = regalloc.force_allocate_reg(op.result, forbidden_vars=[a0, a1])
self.mc.ADD_rr(res.value, l0.value, l1.value, s=1)
- regalloc.possibly_free_vars_for_op(op)
- if op.result:
- regalloc.possibly_free_var(op.result)
+
+ regalloc.possibly_free_var(a0)
+ regalloc.possibly_free_var(a1)
+ regalloc.possibly_free_var(op.result)
return fcond
def emit_op_int_sub(self, op, regalloc, fcond):
@@ -81,9 +82,9 @@
else:
self.mc.SUB_rr(res.value, l0.value, l1.value, s=1)
- regalloc.possibly_free_vars_for_op(op)
- if op.result:
- regalloc.possibly_free_var(op.result)
+ regalloc.possibly_free_var(a0)
+ regalloc.possibly_free_var(a1)
+ regalloc.possibly_free_var(op.result)
return fcond
def emit_op_int_mul(self, op, regalloc, fcond):
@@ -291,21 +292,20 @@
if n_args > 4:
assert n > 0
self._adjust_sp(-n, regalloc, fcond=fcond)
- regalloc.possibly_free_vars(locs)
+ regalloc.possibly_free_vars(args)
return fcond
def emit_op_same_as(self, op, regalloc, fcond):
resloc = regalloc.force_allocate_reg(op.result)
arg = op.getarg(0)
- imm_arg = isinstance(arg, ConstInt) and (arg.getint() <= 0xFF or -1 * arg.getint() <= 0xFF)
- argloc = regalloc.make_sure_var_in_reg(arg, imm_fine=imm_arg)
+ imm_arg = self._check_imm_arg(arg)
+ argloc = regalloc.make_sure_var_in_reg(arg, [op.result], imm_fine=imm_arg)
if argloc.is_imm():
self.mc.MOV_ri(resloc.value, argloc.getint())
else:
self.mc.MOV_rr(resloc.value, argloc.value)
regalloc.possibly_free_vars_for_op(op)
- if op.result:
- regalloc.possibly_free_var(op.result)
+ regalloc.possibly_free_var(op.result)
return fcond
class FieldOpAssembler(object):
@@ -488,8 +488,7 @@
res = regalloc.force_allocate_reg(op.result)
regalloc.possibly_free_vars_for_op(op)
regalloc.possibly_free_var(t)
- if op.result:
- regalloc.possibly_free_var(op.result)
+ regalloc.possibly_free_var(op.result)
basesize, itemsize, ofs_length = symbolic.get_array_token(rstr.STR,
self.cpu.translate_support_code)
@@ -531,8 +530,7 @@
l0 = regalloc.make_sure_var_in_reg(op.getarg(0), imm_fine=False)
regalloc.possibly_free_vars_for_op(op)
res = regalloc.force_allocate_reg(op.result)
- if op.result:
- regalloc.possibly_free_var(op.result)
+ regalloc.possibly_free_var(op.result)
basesize, itemsize, ofs_length = symbolic.get_array_token(rstr.UNICODE,
self.cpu.translate_support_code)
l1 = regalloc.make_sure_var_in_reg(ConstInt(ofs_length))
@@ -693,7 +691,7 @@
offset = self.mc.currpos() - jmp_pos
pmc = ARMv7InMemoryBuilder(jmp_location, WORD)
pmc.ADD_ri(r.pc.value, r.pc.value, offset - PC_OFFSET)
- t = TempBox()
+
l0 = regalloc.force_allocate_reg(t)
self.mc.LDR_ri(l0.value, r.fp.value)
self.mc.CMP_ri(l0.value, 0)
More information about the Pypy-commit
mailing list