[pypy-svn] r79452 - pypy/branch/arm-backend/pypy/jit/backend/arm
david at codespeak.net
david at codespeak.net
Wed Nov 24 13:23:11 CET 2010
Author: david
Date: Wed Nov 24 13:23:09 2010
New Revision: 79452
Modified:
pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py
pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py
pypy/branch/arm-backend/pypy/jit/backend/arm/runner.py
Log:
Fix ops that read fields to correctly zero or one extend the value when it is smaller than a word. Also fix ofset issues with array operations
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py Wed Nov 24 13:23:09 2010
@@ -309,7 +309,7 @@
if self._debug_asm:
self._dump_trace('loop.asm')
- print 'Done assembling'
+ print 'Done assembling loop with token %r' % looptoken
def _prepare_sp_patch_location(self):
"""Generate NOPs as placeholder to patch the instruction(s) to update the
@@ -410,6 +410,27 @@
#XXX check ranges for different operations
return isinstance(arg, ConstInt) and arg.getint() <= size and lower_bound
+
+ def _ensure_result_bit_extension(self, resloc, size, signed, regalloc):
+ if size == 4:
+ return
+ if size == 1:
+ if not signed: #unsigned char
+ self.mc.AND_ri(resloc.value, resloc.value, 0xFF)
+ else:
+ self.mc.LSL_ri(resloc.value, resloc.value, 24)
+ self.mc.ASR_ri(resloc.value, resloc.value, 24)
+ elif size == 2:
+ if not signed:
+ t = TempBox()
+ loc = regalloc.force_allocate_reg(t)
+ self.mc.gen_load_int(loc.value, 0xFFFF)
+ self.mc.AND_rr(resloc.value, resloc.value, loc.value)
+ regalloc.possibly_free_var(t)
+ else:
+ self.mc.LSL_ri(resloc.value, resloc.value, 16)
+ self.mc.ASR_ri(resloc.value, resloc.value, 16)
+
def patch_trace(self, faildescr, bridge_addr, regalloc):
# The first instruction (word) is not overwritten, because it is the
# one that actually checks the condition
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py Wed Nov 24 13:23:09 2010
@@ -251,15 +251,10 @@
descr = op.getdescr()
#XXX Hack, Hack, Hack
if op.result and not we_are_translated() and not isinstance(descr, LoopToken):
- l = regalloc.loc(op.result)
- # XXX we need descr.get_result_sign here!!!!
+ loc = regalloc.loc(op.result)
size = descr.get_result_size(False)
- # for now just check the size of the value
- if size == 1: #unsigned char
- self.mc.AND_ri(l.value, l.value, 255)
- elif size == 2: # signed short
- self.mc.LSL_ri(l.value, l.value, 16)
- self.mc.ASR_ri(l.value, l.value, 16)
+ signed = descr.is_result_signed()
+ self._ensure_result_bit_extension(loc, size, signed, regalloc)
return cond
def _emit_call(self, adr, args, regalloc, fcond=c.AL, save_all_regs=False, result=None):
@@ -353,6 +348,11 @@
else:
assert 0
f(res.value, base_loc.value, ofs)
+
+ #XXX Hack, Hack, Hack
+ if not we_are_translated():
+ signed = op.getdescr().is_field_signed()
+ self._ensure_result_bit_extension(res, size, signed, regalloc)
return fcond
emit_op_getfield_raw = emit_op_getfield_gc
@@ -397,11 +397,14 @@
#XXX check if imm would be fine here
value_loc = regalloc.make_sure_var_in_reg(a2, imm_fine=False)
+ if scale > 0:
+ self.mc.LSL_ri(ofs_loc.value, ofs_loc.value, scale)
+ if ofs > 0:
+ self.mc.ADD_ri(ofs_loc.value, ofs_loc.value, ofs)
+
if scale == 2:
- self.mc.STR_rr(value_loc.value, base_loc.value, ofs_loc.value, cond=fcond,
- imm=scale, shifttype=shift.LSL)
+ self.mc.STR_rr(value_loc.value, base_loc.value, ofs_loc.value, cond=fcond)
elif scale == 1:
- self.mc.LSL_ri(ofs_loc.value, ofs_loc.value, scale)
self.mc.STRH_rr(value_loc.value, base_loc.value, ofs_loc.value, cond=fcond)
elif scale == 0:
self.mc.STRB_rr(value_loc.value, base_loc.value, ofs_loc.value, cond=fcond)
@@ -419,6 +422,12 @@
base_loc = regalloc.make_sure_var_in_reg(a0, imm_fine=False)
ofs_loc = regalloc.make_sure_var_in_reg(a1, imm_fine=False)
res = regalloc.force_allocate_reg(op.result)
+
+ if scale > 0:
+ self.mc.LSL_ri(ofs_loc.value, ofs_loc.value, scale)
+ if ofs > 0:
+ self.mc.ADD_ri(ofs_loc.value, ofs_loc.value, imm=ofs)
+
if scale == 2:
f = self.mc.LDR_rr
elif scale == 1:
@@ -427,9 +436,14 @@
f = self.mc.LDRB_rr
else:
assert 0
- if scale > 0:
- self.mc.LSL_ri(ofs_loc.value, ofs_loc.value, scale)
+
f(res.value, base_loc.value, ofs_loc.value, cond=fcond)
+ #XXX Hack, Hack, Hack
+ if not we_are_translated():
+ descr = op.getdescr()
+ size = descr.get_item_size(False)
+ signed = descr.is_item_signed()
+ self._ensure_result_bit_extension(res, size, signed, regalloc)
return fcond
emit_op_getarrayitem_raw = emit_op_getarrayitem_gc
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/runner.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/runner.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/runner.py Wed Nov 24 13:23:09 2010
@@ -42,7 +42,7 @@
def execute_token(self, executable_token):
i = [self.get_latest_value_int(x) for x in range(10)]
- print 'Inputargs: ', i
+ print 'Inputargs: %r for token %r' % (i, executable_token)
addr = executable_token._arm_bootstrap_code
assert addr % 8 == 0
func = rffi.cast(lltype.Ptr(self.BOOTSTRAP_TP), addr)
More information about the Pypy-commit
mailing list