[pypy-svn] r78697 - in pypy/branch/arm-backend/pypy/jit/backend/arm: . helper
david at codespeak.net
david at codespeak.net
Thu Nov 4 17:33:22 CET 2010
Author: david
Date: Thu Nov 4 17:33:20 2010
New Revision: 78697
Modified:
pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py
pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py
pypy/branch/arm-backend/pypy/jit/backend/arm/helper/assembler.py
pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py
pypy/branch/arm-backend/pypy/jit/backend/arm/regalloc.py
pypy/branch/arm-backend/pypy/jit/backend/arm/registers.py
pypy/branch/arm-backend/pypy/jit/backend/arm/runner.py
Log:
Implement CALL operation
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py Thu Nov 4 17:33:20 2010
@@ -225,16 +225,20 @@
if regalloc.frame_manager.frame_depth == 1:
return
n = regalloc.frame_manager.frame_depth*WORD
- if n <= 0xFF:
+ self._adjust_sp(n, cb)
+
+ def _adjust_sp(self, n, cb=None, fcond=c.AL):
+ if cb is None:
+ cb = self.mc
+ if n <= 0xFF and fcond == c.AL:
cb.SUB_ri(r.sp.value, r.sp.value, n)
else:
b = Box()
reg = regalloc.force_allocate_reg(b)
- cb.gen_load_int(reg.value, n)
- cb.SUB_rr(r.sp.value, r.sp.value, reg.value)
+ cb.gen_load_int(reg.value, n, cond=fcond)
+ cb.SUB_rr(r.sp.value, r.sp.value, reg.value, cond=fcond)
regalloc.possibly_free_var(reg)
-
def assemble_bridge(self, faildescr, inputargs, operations):
enc = rffi.cast(rffi.CCHARP, faildescr._failure_recovery_code)
longevity = compute_vars_longevity(inputargs, operations)
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/codebuilder.py Thu Nov 4 17:33:20 2010
@@ -146,27 +146,27 @@
_space_for_jump = 2 * WORD
def writechar(self, char):
- if self.checks and not self._pos < self._size - self._space_for_jump:
- self.checks = False
+ if self.checks and not self._pos < self._size - self._space_for_jump - WORD:
self._add_more_mem()
- self.checks = True
- assert self._pos < self._size
+ assert self._pos < self._size - 1
AbstractARMv7Builder.writechar(self, char)
def _add_more_mem(self):
+ self.checks = False
new_mem = alloc(self._size)
new_mem_addr = rffi.cast(lltype.Signed, new_mem)
self.LDR_ri(reg.pc.value, reg.pc.value, -4)
self.write32(new_mem_addr)
- self._dump_trace('data%d.asm' % self.n_data)
+ self._dump_trace('data%04d.asm' % self.n_data)
self.n_data += 1
self._data = new_mem
self._pos = 0
+ self.checks = True
def ensure_can_fit(self, n):
"""ensure after this call there is enough space for n instructions
in a contiguous memory chunk"""
- if not self._pos + n + self._space_for_jump < self._size:
+ if not self._pos + n + self._space_for_jump < self._size - WORD:
self._add_more_mem()
define_instructions(AbstractARMv7Builder)
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/helper/assembler.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/helper/assembler.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/helper/assembler.py Thu Nov 4 17:33:20 2010
@@ -47,9 +47,8 @@
arg2 = regalloc.make_sure_var_in_reg(op.getarg(1), selected_reg=r.r1, imm_fine=False)
assert arg1 == r.r0
assert arg2 == r.r1
- res = regalloc.force_allocate_reg(op.result)
+ res = regalloc.force_allocate_reg(op.result, selected_reg=r.r0)
getattr(self.mc, opname)(fcond)
- self.mc.MOV_rr(res.value, r.r0.value, cond=fcond)
regalloc.possibly_free_vars_for_op(op)
return fcond
return f
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py Thu Nov 4 17:33:20 2010
@@ -10,7 +10,7 @@
gen_emit_op_ri, gen_emit_cmp_op)
from pypy.jit.backend.arm.codebuilder import ARMv7Builder, ARMv7InMemoryBuilder
from pypy.jit.backend.arm.regalloc import ARMRegisterManager
-from pypy.jit.backend.llsupport.regalloc import compute_vars_longevity
+from pypy.jit.backend.llsupport.regalloc import compute_vars_longevity, TempBox
from pypy.jit.metainterp.history import ConstInt, BoxInt, Box, BasicFailDescr
from pypy.jit.metainterp.resoperation import rop
from pypy.rlib import rgc
@@ -193,3 +193,29 @@
def emit_op_finish(self, op, regalloc, fcond):
self._gen_path_to_exit_path(op, op.getarglist(), regalloc, c.AL)
return fcond
+
+ def emit_op_call(self, op, regalloc, fcond):
+ locs = []
+ # all arguments past the 4th go on the stack
+ # XXX support types other than int (one word types)
+ if op.numargs() > 5:
+ stack_args = op.numargs() - 5
+ n = stack_args*WORD
+ self._adjust_sp(n, fcond=fcond)
+ for i in range(5, op.numargs()):
+ reg = regalloc.make_sure_var_in_reg(op.getarg(i))
+ self.mc.STR_ri(reg.value, r.sp.value, (i-5)*WORD)
+ regalloc.possibly_free_var(reg)
+
+ adr = self.cpu.cast_adr_to_int(op.getarg(0).getint())
+ regalloc.before_call()
+
+ reg_args = min(op.numargs()-1, 4)
+ for i in range(1, reg_args+1):
+ l = regalloc.make_sure_var_in_reg(op.getarg(i),
+ selected_reg=r.all_regs[i-1])
+ locs.append(l)
+ self.mc.BL(adr)
+ regalloc.force_allocate_reg(op.result, selected_reg=r.r0)
+ regalloc.after_call(op.result)
+ regalloc.possibly_free_vars(locs)
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/regalloc.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/regalloc.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/regalloc.py Thu Nov 4 17:33:20 2010
@@ -7,7 +7,7 @@
all_regs = r.all_regs
box_types = None # or a list of acceptable types
no_lower_byte_regs = all_regs
- save_around_call_regs = all_regs
+ save_around_call_regs = r.caller_resp
def __init__(self, longevity, frame_manager=None, assembler=None):
RegisterManager.__init__(self, longevity, frame_manager, assembler)
@@ -24,6 +24,9 @@
def convert_to_imm(self, c):
return locations.ImmLocation(c.value)
+ def call_result_location(self, v):
+ return r.r0
+
class ARMFrameManager(FrameManager):
def __init__(self):
FrameManager.__init__(self)
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/registers.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/registers.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/registers.py Thu Nov 4 17:33:20 2010
@@ -10,8 +10,9 @@
lr = r14
pc = r15
-all_regs = registers[:11]
+all_regs = [r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10]
+caller_resp = [r0, r1, r2, r3]
callee_resp = [r4, r5, r6, r7, r8, r9, r10, r11]
callee_saved_registers = callee_resp+[lr]
callee_restored_registers = callee_resp+[pc]
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/runner.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/runner.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/runner.py Thu Nov 4 17:33:20 2010
@@ -1,7 +1,7 @@
from pypy.jit.backend.arm.assembler import AssemblerARM
from pypy.jit.backend.llsupport.llmodel import AbstractLLCPU
from pypy.rpython.llinterp import LLInterpreter
-from pypy.rpython.lltypesystem import lltype, rffi
+from pypy.rpython.lltypesystem import lltype, rffi, llmemory
class ArmCPU(AbstractLLCPU):
@@ -51,3 +51,7 @@
# LLInterpreter.current_interpreter = prev_interpreter
return res
+ @staticmethod
+ def cast_ptr_to_int(x):
+ adr = llmemory.cast_ptr_to_adr(x)
+ return self.cast_adr_to_int(adr)
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