[pypy-svn] r74792 - in pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86: . test
jcreigh at codespeak.net
jcreigh at codespeak.net
Wed May 26 20:29:52 CEST 2010
Author: jcreigh
Date: Wed May 26 20:29:49 2010
New Revision: 74792
Modified:
pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/assembler.py
pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/regloc.py
pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/rx86.py
pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86.py
pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86_32_auto_encoding.py
Log:
add new 'x' code to rx86 to indicate an xmm register instead of using 'r'. This makes automated testing easier and makes instructions like CVTSI2SD_xr clearer
Modified: pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/assembler.py
==============================================================================
--- pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/assembler.py (original)
+++ pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/assembler.py Wed May 26 20:29:49 2010
@@ -202,7 +202,7 @@
self.malloc_fixedsize_slowpath1 = mc.tell()
if self.cpu.supports_floats: # save the XMM registers in
for i in range(8): # the *caller* frame, from esp+8
- mc.MOVSD_sr(8+8*i, i)
+ mc.MOVSD_sx(8+8*i, i)
mc.SUB(edx, eax) # compute the size we want
mc.MOV_sr(4, edx.value) # save it as the new argument
addr = self.cpu.gc_ll_descr.get_malloc_fixedsize_slowpath_addr()
@@ -211,7 +211,7 @@
self.malloc_fixedsize_slowpath2 = mc.tell()
if self.cpu.supports_floats: # restore the XMM registers
for i in range(8): # from where they were saved
- mc.MOVSD_rs(i, 8+8*i)
+ mc.MOVSD_xs(i, 8+8*i)
nursery_free_adr = self.cpu.gc_ll_descr.get_nursery_free_addr()
mc.MOV(edx, heap(nursery_free_adr)) # load this in EDX
mc.RET()
@@ -370,7 +370,7 @@
loc = floatlocs[i]
if isinstance(loc, RegLoc):
assert loc.is_xmm
- self.mc.MOVSD_rb(loc.value, (1 + i) * 2 * WORD)
+ self.mc.MOVSD_xb(loc.value, (1 + i) * 2 * WORD)
tmp = eax
xmmtmp = xmm0
for i in range(len(nonfloatlocs)):
@@ -380,9 +380,9 @@
self.mc.MOV(loc, tmp)
loc = floatlocs[i]
if loc is not None and not isinstance(loc, RegLoc):
- self.mc.MOVSD_rb(xmmtmp.value, (1 + i) * 2 * WORD)
+ self.mc.MOVSD_xb(xmmtmp.value, (1 + i) * 2 * WORD)
assert isinstance(loc, StackLoc)
- self.mc.MOVSD_br(loc.value, xmmtmp.value)
+ self.mc.MOVSD_bx(loc.value, xmmtmp.value)
self.mc.JMP_l(jmpadr)
return adr_stackadjust
@@ -417,11 +417,11 @@
continue
adr = self.fail_boxes_float.get_addr_for_num(i)
if isinstance(loc, RegLoc):
- self.mc.MOVSD_rj(loc.value, adr)
+ self.mc.MOVSD_xj(loc.value, adr)
else:
- self.mc.MOVSD_rj(xmmtmp.value, adr)
+ self.mc.MOVSD_xj(xmmtmp.value, adr)
assert isinstance(loc, StackLoc)
- self.mc.MOVSD_br(loc.value, xmmtmp.value)
+ self.mc.MOVSD_bx(loc.value, xmmtmp.value)
return adr_stackadjust
def dump(self, text):
@@ -464,7 +464,7 @@
def regalloc_push(self, loc):
if isinstance(loc, RegLoc) and loc.is_xmm:
self.mc.SUB_ri(esp.value, 2*WORD)
- self.mc.MOVSD_sr(0, loc.value)
+ self.mc.MOVSD_sx(0, loc.value)
elif isinstance(loc, StackLoc) and loc.width == 8:
# XXX evil trick
self.mc.PUSH_b(get_ebp_ofs(loc.position))
@@ -474,7 +474,7 @@
def regalloc_pop(self, loc):
if isinstance(loc, RegLoc) and loc.is_xmm:
- self.mc.MOVSD_rs(loc.value, 0)
+ self.mc.MOVSD_xs(loc.value, 0)
self.mc.ADD(esp, imm(2*WORD))
elif isinstance(loc, StackLoc) and loc.width == 8:
# XXX evil trick
@@ -600,7 +600,7 @@
loc = arglocs[i]
if isinstance(loc, RegLoc):
if loc.is_xmm:
- mc.MOVSD_sr(p, loc.value)
+ mc.MOVSD_sx(p, loc.value)
else:
mc.MOV_sr(p, loc.value)
p += round_up_to_4(loc.width)
@@ -610,7 +610,7 @@
if not isinstance(loc, RegLoc):
if loc.width == 8:
mc.MOVSD(xmm0, loc)
- mc.MOVSD_sr(p, xmm0.value)
+ mc.MOVSD_sx(p, xmm0.value)
else:
mc.MOV(tmp, loc)
mc.MOV_sr(p, tmp.value)
@@ -696,16 +696,16 @@
def genop_float_neg(self, op, arglocs, resloc):
# Following what gcc does: res = x ^ 0x8000000000000000
- self.mc.XORPD_rj(arglocs[0].value, self.loc_float_const_neg)
+ self.mc.XORPD_xj(arglocs[0].value, self.loc_float_const_neg)
def genop_float_abs(self, op, arglocs, resloc):
# Following what gcc does: res = x & 0x7FFFFFFFFFFFFFFF
- self.mc.ANDPD_rj(arglocs[0].value, self.loc_float_const_abs)
+ self.mc.ANDPD_xj(arglocs[0].value, self.loc_float_const_abs)
def genop_guard_float_is_true(self, op, guard_op, addr, arglocs, resloc):
guard_opnum = guard_op.opnum
loc0, loc1 = arglocs
- self.mc.XORPD_rr(loc0.value, loc0.value)
+ self.mc.XORPD_xx(loc0.value, loc0.value)
self.mc.UCOMISD(loc0, loc1)
mc = self.mc._mc
if guard_opnum == rop.GUARD_TRUE:
@@ -718,7 +718,7 @@
return self.implement_guard(addr)
def genop_float_is_true(self, op, arglocs, resloc):
- self.mc.XORPD_rr(arglocs[0].value, arglocs[0].value)
+ self.mc.XORPD_xx(arglocs[0].value, arglocs[0].value)
self.genop_float_ne(op, arglocs, resloc)
def genop_cast_float_to_int(self, op, arglocs, resloc):
@@ -1294,7 +1294,7 @@
if withfloats:
mc.SUB_ri(esp.value, 8*8)
for i in range(8):
- mc.MOVSD_sr(8*i, i)
+ mc.MOVSD_sx(8*i, i)
# we call a provided function that will
# - call our on_leave_jitted_hook which will mark
@@ -1335,7 +1335,7 @@
if isinstance(loc, RegLoc):
if loc.width == 8:
adr = self.fail_boxes_float.get_addr_for_num(i)
- mc.MOVSD_jr(adr, loc.value)
+ mc.MOVSD_jx(adr, loc.value)
else:
if locs_are_ref[i]:
adr = self.fail_boxes_ptr.get_addr_for_num(i)
@@ -1347,9 +1347,9 @@
if not isinstance(loc, RegLoc):
if loc.width == 8:
assert isinstance(loc, StackLoc)
- mc.MOVSD_rb(xmm0.value, loc.value)
+ mc.MOVSD_xb(xmm0.value, loc.value)
adr = self.fail_boxes_float.get_addr_for_num(i)
- mc.MOVSD_jr(adr, xmm0.value)
+ mc.MOVSD_jx(adr, xmm0.value)
else:
if locs_are_ref[i]:
adr = self.fail_boxes_ptr.get_addr_for_num(i)
Modified: pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/regloc.py
==============================================================================
--- pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/regloc.py (original)
+++ pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/regloc.py Wed May 26 20:29:49 2010
@@ -59,7 +59,10 @@
return RegLoc(rx86.high_byte(self.value), False)
def location_code(self):
- return 'r'
+ if self.is_xmm:
+ return 'x'
+ else:
+ return 'r'
# FIXME: This definition of assembler sufficient?
def assembler(self):
Modified: pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/rx86.py
==============================================================================
--- pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/rx86.py (original)
+++ pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/rx86.py Wed May 26 20:29:49 2010
@@ -529,58 +529,56 @@
# ------------------------------ SSE2 ------------------------------
- MOVSD_rr = xmminsn('\xF2', rex_nw, '\x0F\x10', register(1,8), register(2),
+ MOVSD_xx = xmminsn('\xF2', rex_nw, '\x0F\x10', register(1,8), register(2),
'\xC0')
- MOVSD_rb = xmminsn('\xF2', rex_nw, '\x0F\x10', register(1,8), stack_bp(2))
- MOVSD_br = xmminsn('\xF2', rex_nw, '\x0F\x11', register(2,8), stack_bp(1))
- MOVSD_rs = xmminsn('\xF2', rex_nw, '\x0F\x10', register(1,8), stack_sp(2))
- MOVSD_sr = xmminsn('\xF2', rex_nw, '\x0F\x11', register(2,8), stack_sp(1))
- MOVSD_rm = xmminsn('\xF2', rex_nw, '\x0F\x10', register(1,8),
+ MOVSD_xb = xmminsn('\xF2', rex_nw, '\x0F\x10', register(1,8), stack_bp(2))
+ MOVSD_bx = xmminsn('\xF2', rex_nw, '\x0F\x11', register(2,8), stack_bp(1))
+ MOVSD_xs = xmminsn('\xF2', rex_nw, '\x0F\x10', register(1,8), stack_sp(2))
+ MOVSD_sx = xmminsn('\xF2', rex_nw, '\x0F\x11', register(2,8), stack_sp(1))
+ MOVSD_xm = xmminsn('\xF2', rex_nw, '\x0F\x10', register(1,8),
mem_reg_plus_const(2))
- MOVSD_ra = xmminsn('\xF2', rex_nw, '\x0F\x10', register(1,8), mem_reg_plus_scaled_reg_plus_const(2))
- MOVSD_mr = xmminsn('\xF2', rex_nw, '\x0F\x11', register(2,8),
+ MOVSD_xa = xmminsn('\xF2', rex_nw, '\x0F\x10', register(1,8), mem_reg_plus_scaled_reg_plus_const(2))
+ MOVSD_mx = xmminsn('\xF2', rex_nw, '\x0F\x11', register(2,8),
mem_reg_plus_const(1))
- MOVSD_ar = xmminsn('\xF2', rex_nw, '\x0F\x11', register(2,8), mem_reg_plus_scaled_reg_plus_const(1))
+ MOVSD_ax = xmminsn('\xF2', rex_nw, '\x0F\x11', register(2,8), mem_reg_plus_scaled_reg_plus_const(1))
- MOVSD_rj = xmminsn('\xF2', rex_nw, '\x0F\x10', register(1, 8), '\x05', immediate(2))
- MOVSD_jr = xmminsn('\xF2', rex_nw, '\x0F\x11', register(2, 8), '\x05', immediate(1))
+ MOVSD_xj = xmminsn('\xF2', rex_nw, '\x0F\x10', register(1, 8), '\x05', immediate(2))
+ MOVSD_jx = xmminsn('\xF2', rex_nw, '\x0F\x11', register(2, 8), '\x05', immediate(1))
# Arithmetic
- ADDSD_rr = xmminsn('\xF2', rex_nw, '\x0F\x58', register(1, 8), register(2), '\xC0')
- ADDSD_rb = xmminsn('\xF2', rex_nw, '\x0F\x58', register(1, 8), stack_bp(2))
- ADDSD_rj = xmminsn('\xF2', rex_nw, '\x0F\x58', register(1, 8), '\x05', immediate(2))
-
- SUBSD_rr = xmminsn('\xF2', rex_nw, '\x0F\x5C', register(1, 8), register(2), '\xC0')
- SUBSD_rb = xmminsn('\xF2', rex_nw, '\x0F\x5C', register(1, 8), stack_bp(2))
- SUBSD_rj = xmminsn('\xF2', rex_nw, '\x0F\x5C', register(1, 8), '\x05', immediate(2))
-
- MULSD_rr = xmminsn('\xF2', rex_nw, '\x0F\x59', register(1, 8), register(2), '\xC0')
- MULSD_rb = xmminsn('\xF2', rex_nw, '\x0F\x59', register(1, 8), stack_bp(2))
- MULSD_rj = xmminsn('\xF2', rex_nw, '\x0F\x59', register(1, 8), '\x05', immediate(2))
-
- DIVSD_rr = xmminsn('\xF2', rex_nw, '\x0F\x5E', register(1, 8), register(2), '\xC0')
- DIVSD_rb = xmminsn('\xF2', rex_nw, '\x0F\x5E', register(1, 8), stack_bp(2))
- DIVSD_rj = xmminsn('\xF2', rex_nw, '\x0F\x5E', register(1, 8), '\x05', immediate(2))
+ ADDSD_xx = xmminsn('\xF2', rex_nw, '\x0F\x58', register(1, 8), register(2), '\xC0')
+ ADDSD_xb = xmminsn('\xF2', rex_nw, '\x0F\x58', register(1, 8), stack_bp(2))
+ ADDSD_xj = xmminsn('\xF2', rex_nw, '\x0F\x58', register(1, 8), '\x05', immediate(2))
+
+ SUBSD_xx = xmminsn('\xF2', rex_nw, '\x0F\x5C', register(1, 8), register(2), '\xC0')
+ SUBSD_xb = xmminsn('\xF2', rex_nw, '\x0F\x5C', register(1, 8), stack_bp(2))
+ SUBSD_xj = xmminsn('\xF2', rex_nw, '\x0F\x5C', register(1, 8), '\x05', immediate(2))
+
+ MULSD_xx = xmminsn('\xF2', rex_nw, '\x0F\x59', register(1, 8), register(2), '\xC0')
+ MULSD_xb = xmminsn('\xF2', rex_nw, '\x0F\x59', register(1, 8), stack_bp(2))
+ MULSD_xj = xmminsn('\xF2', rex_nw, '\x0F\x59', register(1, 8), '\x05', immediate(2))
+
+ DIVSD_xx = xmminsn('\xF2', rex_nw, '\x0F\x5E', register(1, 8), register(2), '\xC0')
+ DIVSD_xb = xmminsn('\xF2', rex_nw, '\x0F\x5E', register(1, 8), stack_bp(2))
+ DIVSD_xj = xmminsn('\xF2', rex_nw, '\x0F\x5E', register(1, 8), '\x05', immediate(2))
# Comparision
- UCOMISD_rr = xmminsn('\x66', rex_nw, '\x0F\x2E', register(1, 8), register(2), '\xC0')
- UCOMISD_rb = xmminsn('\x66', rex_nw, '\x0F\x2E', register(1, 8), stack_bp(2))
- UCOMISD_rj = xmminsn('\x66', rex_nw, '\x0F\x2E', register(1, 8), '\x05', immediate(2))
+ UCOMISD_xx = xmminsn('\x66', rex_nw, '\x0F\x2E', register(1, 8), register(2), '\xC0')
+ UCOMISD_xb = xmminsn('\x66', rex_nw, '\x0F\x2E', register(1, 8), stack_bp(2))
+ UCOMISD_xj = xmminsn('\x66', rex_nw, '\x0F\x2E', register(1, 8), '\x05', immediate(2))
# Conversion
- # FIXME: Super confusing! The source is a GPR/mem, the destination is an xmm register
- # (and the same goes for SD2SI too)
- CVTSI2SD_rr = xmminsn('\xF2', rex_nw, '\x0F\x2A', register(1, 8), register(2), '\xC0')
- CVTSI2SD_rb = xmminsn('\xF2', rex_nw, '\x0F\x2A', register(1, 8), stack_bp(2))
+ CVTSI2SD_xr = xmminsn('\xF2', rex_w, '\x0F\x2A', register(1, 8), register(2), '\xC0')
+ CVTSI2SD_xb = xmminsn('\xF2', rex_w, '\x0F\x2A', register(1, 8), stack_bp(2))
- CVTTSD2SI_rr = xmminsn('\xF2', rex_nw, '\x0F\x2C', register(1, 8), register(2), '\xC0')
- CVTTSD2SI_rb = xmminsn('\xF2', rex_nw, '\x0F\x2C', register(1, 8), stack_bp(2))
+ CVTTSD2SI_rx = xmminsn('\xF2', rex_w, '\x0F\x2C', register(1, 8), register(2), '\xC0')
+ CVTTSD2SI_rb = xmminsn('\xF2', rex_w, '\x0F\x2C', register(1, 8), stack_bp(2))
# Bitwise
- ANDPD_rj = xmminsn('\x66', rex_nw, '\x0F\x54', register(1, 8), '\x05', immediate(2))
+ ANDPD_xj = xmminsn('\x66', rex_nw, '\x0F\x54', register(1, 8), '\x05', immediate(2))
- XORPD_rr = xmminsn('\x66', rex_nw, '\x0F\x57', register(1, 8), register(2), '\xC0')
- XORPD_rj = xmminsn('\x66', rex_nw, '\x0F\x57', register(1, 8), '\x05', immediate(2))
+ XORPD_xx = xmminsn('\x66', rex_nw, '\x0F\x57', register(1, 8), register(2), '\xC0')
+ XORPD_xj = xmminsn('\x66', rex_nw, '\x0F\x57', register(1, 8), '\x05', immediate(2))
# ------------------------------------------------------------
@@ -656,23 +654,23 @@
py.test.skip("CMP_ji unsupported")
def CMP_rj(self, reg, immed):
py.test.skip("CMP_rj unsupported")
- def MOVSD_rj(self, xmm_reg, mem_immed):
+ def MOVSD_xj(self, xmm_reg, mem_immed):
py.test.skip("MOVSD_rj unsupported")
- def MOVSD_jr(self, xmm_reg, mem_immed):
+ def MOVSD_jx(self, xmm_reg, mem_immed):
py.test.skip("MOVSD_jr unsupported")
- def ADDSD_rj(self, xmm_reg, mem_immed):
+ def ADDSD_xj(self, xmm_reg, mem_immed):
py.test.skip("ADDSD_rj unsupported")
- def SUBSD_rj(self, xmm_reg, mem_immed):
+ def SUBSD_xj(self, xmm_reg, mem_immed):
py.test.skip("SUBSD_rj unsupported")
- def MULSD_rj(self, xmm_reg, mem_immed):
+ def MULSD_xj(self, xmm_reg, mem_immed):
py.test.skip("MULSD_rj unsupported")
- def DIVSD_rj(self, xmm_reg, mem_immed):
+ def DIVSD_xj(self, xmm_reg, mem_immed):
py.test.skip("DIVSD_rj unsupported")
- def UCOMISD_rj(self, xmm_reg, mem_immed):
+ def UCOMISD_xj(self, xmm_reg, mem_immed):
py.test.skip("UCOMISD_rj unsupported")
- def ANDPD_rj(self, xmm_reg, mem_immed):
+ def ANDPD_xj(self, xmm_reg, mem_immed):
py.test.skip("ANDPD_rj unsupported")
- def XORPD_rj(self, xmm_reg, mem_immed):
+ def XORPD_xj(self, xmm_reg, mem_immed):
py.test.skip("XORPD_rj unsupported")
Modified: pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86.py
==============================================================================
--- pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86.py (original)
+++ pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86.py Wed May 26 20:29:49 2010
@@ -131,7 +131,7 @@
def test_movsd_rj():
s = CodeBuilder32()
- s.MOVSD_rj(xmm2, 0x01234567)
+ s.MOVSD_xj(xmm2, 0x01234567)
assert s.getvalue() == '\xF2\x0F\x10\x15\x67\x45\x23\x01'
def test_movzx8_rm():
Modified: pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86_32_auto_encoding.py
==============================================================================
--- pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86_32_auto_encoding.py (original)
+++ pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86_32_auto_encoding.py Wed May 26 20:29:49 2010
@@ -52,6 +52,9 @@
def reg_tests(self):
return self.REGS
+ def xmm_reg_tests(self):
+ return self.reg_tests()
+
def stack_bp_tests(self, count=COUNT1):
return ([0, 4, -4, 124, 128, -128, -132] +
[random.randrange(-0x20000000, 0x20000000) * 4
@@ -94,6 +97,7 @@
def get_all_tests(self):
return {
'r': self.reg_tests,
+ 'x': self.xmm_reg_tests,
'b': self.stack_bp_tests,
's': self.stack_sp_tests,
'm': self.memory_tests,
@@ -104,10 +108,10 @@
}
def assembler_operand_reg(self, regnum):
- if self.is_xmm_insn:
- return self.XMMREGNAMES[regnum]
- else:
- return self.REGNAMES[regnum]
+ return self.REGNAMES[regnum]
+
+ def assembler_operand_xmm_reg(self, regnum):
+ return self.XMMREGNAMES[regnum]
def assembler_operand_stack_bp(self, position):
return '%d(%s)' % (position, self.REGNAMES[5])
@@ -133,6 +137,7 @@
def get_all_assembler_operands(self):
return {
'r': self.assembler_operand_reg,
+ 'x': self.assembler_operand_xmm_reg,
'b': self.assembler_operand_stack_bp,
's': self.assembler_operand_stack_sp,
'm': self.assembler_operand_memory,
@@ -158,6 +163,11 @@
## suffix = suffixes[sizes[m]] + suffix
if argmodes and not self.is_xmm_insn:
suffix = suffixes[self.WORD]
+ # Special case: On 64-bit CPUs, rx86 assumes 64-bit integer
+ # operands when converting to/from floating point, so we need to
+ # indicate that with a suffix
+ if (self.WORD == 8) and instrname.startswith('CVT'):
+ suffix = suffixes[self.WORD]
following = ""
if False: # instr.indirect:
@@ -225,10 +235,6 @@
if methname.startswith('SHL') or methname.startswith('SAR') or methname.startswith('SHR'):
# XXX: Would be nice to test these automatically
py.test.skip('Shifts must be tested manually')
- if methname.startswith('CVT'):
- # Can't test automatically right now, we don't know
- # which register types to use
- py.test.skip('Skipping CVT instructions for now')
if methname == 'FSTP_b':
# Doesn't work on 64-bit, skipping for now
py.test.skip('Skipping FSTP')
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