[pypy-svn] r74786 - in pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86: . test
jcreigh at codespeak.net
jcreigh at codespeak.net
Wed May 26 19:06:49 CEST 2010
Author: jcreigh
Date: Wed May 26 19:06:47 2010
New Revision: 74786
Modified:
pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/assembler.py
pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/regloc.py
pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/rx86.py
pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_runner.py
pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86.py
pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86_32_auto_encoding.py
Log:
fix some more test failures
Modified: pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/assembler.py
==============================================================================
--- pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/assembler.py (original)
+++ pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/assembler.py Wed May 26 19:06:47 2010
@@ -576,16 +576,15 @@
self.mc.UCOMISD(arglocs[0], arglocs[1])
if guard_opnum == rop.GUARD_FALSE:
mc = self.mc._mc
- name = 'J' + cond
if need_jp:
- mc.JP(rel8(6))
- getattr(mc, name)(rel32(addr))
+ mc.J_il8(rx86.Conditions['P'], 6)
+ mc.J_il(rx86.Conditions[cond], addr)
return mc.tell() - 4
else:
if need_jp:
mc = self.mc._mc
- mc.JP(rel8(2))
- getattr(mc, 'J' + cond)(rel8(5))
+ mc.J_il8(rx86.Conditions['P'], 2)
+ mc.J_il8(rx86.Conditions[cond], 5)
return self.implement_guard(addr)
return self.implement_guard(addr, false_cond)
return genop_cmp_guard_float
@@ -687,12 +686,12 @@
self.mc.UCOMISD(arglocs[0], arglocs[1])
mc = self.mc._mc
if guard_opnum == rop.GUARD_TRUE:
- mc.JP(rel8(6))
- mc.JE(rel32(addr))
+ mc.J_il8(rx86.Conditions['P'], 6)
+ mc.J_il(rx86.Conditions['E'], addr)
return mc.tell() - 4
else:
- mc.JP(rel8(2))
- mc.JE(rel8(5))
+ mc.J_il8(rx86.Conditions['P'], 2)
+ mc.J_il8(rx86.Conditions['E'], 5)
return self.implement_guard(addr)
def genop_float_neg(self, op, arglocs, resloc):
@@ -710,12 +709,12 @@
self.mc.UCOMISD(loc0, loc1)
mc = self.mc._mc
if guard_opnum == rop.GUARD_TRUE:
- mc.JP(rel8(6))
- mc.JZ(rel32(addr))
+ mc.J_il8(rx86.Conditions['P'], 6)
+ mc.J_il(rx86.Conditions['Z'], addr)
return mc.tell() - 4
else:
- mc.JP(rel8(2))
- mc.JZ(rel8(5))
+ mc.J_il8(rx86.Conditions['P'], 2)
+ mc.J_il8(rx86.Conditions['Z'], 5)
return self.implement_guard(addr)
def genop_float_is_true(self, op, arglocs, resloc):
@@ -832,7 +831,7 @@
scale.value))
else:
if scale.value == 0:
- self.mc.MOVZX(resloc, addr8_add(base_loc, ofs_loc, ofs.value,
+ self.mc.MOVZX8(resloc, addr8_add(base_loc, ofs_loc, ofs.value,
scale.value))
elif scale.value == 2:
self.mc.MOV(resloc, addr_add(base_loc, ofs_loc, ofs.value,
@@ -1402,7 +1401,7 @@
self._emit_call(x, arglocs, 2, tmp=tmp)
if isinstance(resloc, StackLoc) and resloc.width == 8:
- self.mc.FSTP(resloc)
+ self.mc.FSTP_b(resloc.value)
elif size == 1:
self.mc.AND(eax, imm(0xff))
elif size == 2:
@@ -1446,7 +1445,7 @@
mc.overwrite(jmp_location - 1, [chr(offset)])
self._stop_block()
if isinstance(result_loc, StackLoc) and result_loc.width == 8:
- self.mc.FSTP(result_loc)
+ self.mc.FSTP_b(result_loc.value)
else:
assert result_loc is eax or result_loc is None
self.mc.CMP_bi(FORCE_INDEX_OFS, 0)
@@ -1461,8 +1460,8 @@
assert cls is not None and isinstance(descr, cls)
loc_base = arglocs[0]
mc = self._start_block()
- mc.TEST(mem8(loc_base, descr.jit_wb_if_flag_byteofs),
- imm8(descr.jit_wb_if_flag_singlebyte))
+ mc.TEST8_mi((loc_base.value, descr.jit_wb_if_flag_byteofs),
+ descr.jit_wb_if_flag_singlebyte)
mc.J_il8(rx86.Conditions['Z'], 0) # patched later
jz_location = mc.get_relative_pos()
# the following is supposed to be the slow path, so whenever possible
@@ -1475,7 +1474,7 @@
mc.CALL_l(descr.get_write_barrier_fn(self.cpu))
for i in range(len(arglocs)):
loc = arglocs[i]
- assert isinstance(loc, REG)
+ assert isinstance(loc, RegLoc)
mc.POP(loc)
# patch the JZ above
offset = mc.get_relative_pos() - jz_location
@@ -1579,6 +1578,8 @@
def addr_add(reg_or_imm1, reg_or_imm2, offset=0, scale=0):
return AddressLoc(reg_or_imm1, reg_or_imm2, scale, offset)
+addr64_add = addr_add
+addr8_add = addr_add
def addr_add_const(reg_or_imm1, offset):
return AddressLoc(reg_or_imm1, ImmedLoc(0), 0, offset)
Modified: pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/regloc.py
==============================================================================
--- pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/regloc.py (original)
+++ pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/regloc.py Wed May 26 19:06:47 2010
@@ -81,6 +81,12 @@
def __repr__(self):
return "ImmedLoc(%d)" % (self.value)
+ def lowest8bits(self):
+ # XXX: Maybe we could just truncate? But I'm not sure when that
+ # would be the correct behavior.
+ assert rx86.single_byte(self.value)
+ return self
+
class AddressLoc(AssemblerLocation):
_immutable_ = True
@@ -96,7 +102,7 @@
self.value = base_loc.value + (scaled_loc.value << scale) + static_offset
else:
self._location_code = 'a'
- self.value = (None, scaled_loc.value, scale, static_offset)
+ self.value = (None, scaled_loc.value, scale, base_loc.value + static_offset)
else:
if isinstance(scaled_loc, ImmedLoc):
# FIXME: What if base_loc is ebp or esp?
@@ -134,15 +140,16 @@
getattr(self, name + '_' + loc.location_code())(loc.value)
return INSN
- ADD = _binaryop('ADD')
+ AND = _binaryop('AND')
OR = _binaryop('OR')
XOR = _binaryop('XOR')
+ NOT = _unaryop('NOT')
SHL = _binaryop('SHL')
SHR = _binaryop('SHR')
SAR = _binaryop('SAR')
TEST = _binaryop('TEST')
- AND = _binaryop('AND')
+ ADD = _binaryop('ADD')
SUB = _binaryop('SUB')
IMUL = _binaryop('IMUL')
NEG = _unaryop('NEG')
@@ -153,6 +160,9 @@
MOVZX8 = _binaryop('MOVZX8')
MOVZX16 = _binaryop('MOVZX16')
+ PUSH = _unaryop("PUSH")
+ POP = _unaryop("POP")
+
LEA = _binaryop('LEA')
MOVSD = _binaryop('MOVSD')
@@ -162,6 +172,7 @@
DIVSD = _binaryop('DIVSD')
UCOMISD = _binaryop('UCOMISD')
CVTSI2SD = _binaryop('CVTSI2SD')
+ CVTTSD2SI = _binaryop('CVTTSD2SI')
def CALL(self, loc):
@@ -177,14 +188,6 @@
self.writechar('\x66')
self.MOV(dest_loc, src_loc)
- def PUSH(self, loc):
- assert isinstance(loc, RegLoc)
- self.PUSH_r(loc.value)
-
- def POP(self, loc):
- assert isinstance(loc, RegLoc)
- self.POP_r(loc.value)
-
def CMPi(self, loc0, loc1):
# like CMP, but optimized for the case of loc1 being a Const
assert isinstance(loc1, Const)
Modified: pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/rx86.py
==============================================================================
--- pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/rx86.py (original)
+++ pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/rx86.py Wed May 26 19:06:47 2010
@@ -429,6 +429,9 @@
MOV_ji = insn(rex_w, '\xC7', '\x05', immediate(1), immediate(2))
MOV8_mr = insn(rex_w, '\x88', byte_register(2, 8), mem_reg_plus_const(1))
+ MOV8_ar = insn(rex_w, '\x88', byte_register(2, 8), mem_reg_plus_scaled_reg_plus_const(1))
+ MOV8_mi = insn(rex_w, '\xC6', orbyte(0<<3), mem_reg_plus_const(1), immediate(2, 'b'))
+ MOV8_ai = insn(rex_w, '\xC6', orbyte(0<<3), mem_reg_plus_scaled_reg_plus_const(1), immediate(2, 'b'))
MOVZX8_rr = insn(rex_w, '\x0F\xB6', register(1,8), byte_register(2), '\xC0')
MOVZX8_rm = insn(rex_w, '\x0F\xB6', register(1,8), mem_reg_plus_const(2))
@@ -479,6 +482,9 @@
SHR_ri, SHR_rr = shifts(5)
SAR_ri, SAR_rr = shifts(7)
+ NOT_r = insn(rex_w, '\xF7', register(1), '\xD0')
+ NOT_b = insn(rex_w, '\xF7', orbyte(2<<3), stack_bp(1))
+
# ------------------------------ Misc stuff ------------------------------
NOP = insn('\x90')
@@ -515,8 +521,12 @@
# The 64-bit version of this, CQO, is defined in X86_64_CodeBuilder
CDQ = insn(rex_nw, '\x99')
+ TEST8_mi = insn(rex_w, '\xF6', orbyte(0<<3), mem_reg_plus_const(1), immediate(2, 'b'))
TEST_rr = insn(rex_w, '\x85', register(2,8), register(1), '\xC0')
+ # x87 instructions
+ FSTP_b = insn('\xDD', orbyte(3<<3), stack_bp(1))
+
# ------------------------------ SSE2 ------------------------------
MOVSD_rr = xmminsn('\xF2', rex_nw, '\x0F\x10', register(1,8), register(2),
@@ -527,8 +537,10 @@
MOVSD_sr = xmminsn('\xF2', rex_nw, '\x0F\x11', register(2,8), stack_sp(1))
MOVSD_rm = xmminsn('\xF2', rex_nw, '\x0F\x10', register(1,8),
mem_reg_plus_const(2))
+ MOVSD_ra = xmminsn('\xF2', rex_nw, '\x0F\x10', register(1,8), mem_reg_plus_scaled_reg_plus_const(2))
MOVSD_mr = xmminsn('\xF2', rex_nw, '\x0F\x11', register(2,8),
mem_reg_plus_const(1))
+ MOVSD_ar = xmminsn('\xF2', rex_nw, '\x0F\x11', register(2,8), mem_reg_plus_scaled_reg_plus_const(1))
MOVSD_rj = xmminsn('\xF2', rex_nw, '\x0F\x10', register(1, 8), '\x05', immediate(2))
MOVSD_jr = xmminsn('\xF2', rex_nw, '\x0F\x11', register(2, 8), '\x05', immediate(1))
@@ -557,9 +569,13 @@
# Conversion
# FIXME: Super confusing! The source is a GPR/mem, the destination is an xmm register
+ # (and the same goes for SD2SI too)
CVTSI2SD_rr = xmminsn('\xF2', rex_nw, '\x0F\x2A', register(1, 8), register(2), '\xC0')
CVTSI2SD_rb = xmminsn('\xF2', rex_nw, '\x0F\x2A', register(1, 8), stack_bp(2))
+ CVTTSD2SI_rr = xmminsn('\xF2', rex_nw, '\x0F\x2C', register(1, 8), register(2), '\xC0')
+ CVTTSD2SI_rb = xmminsn('\xF2', rex_nw, '\x0F\x2C', register(1, 8), stack_bp(2))
+
# Bitwise
ANDPD_rj = xmminsn('\x66', rex_nw, '\x0F\x54', register(1, 8), '\x05', immediate(2))
Modified: pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_runner.py
==============================================================================
--- pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_runner.py (original)
+++ pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_runner.py Wed May 26 19:06:47 2010
@@ -71,6 +71,9 @@
return ctypes.cast(buf, ctypes.c_void_p).value
func = ctypes.CFUNCTYPE(ctypes.c_int, ctypes.c_int)(f)
addr = ctypes.cast(func, ctypes.c_void_p).value
+ # ctypes produces an unsigned value. We need it to be signed for, eg,
+ # relative addressing to work properly.
+ addr = rffi.cast(lltype.Signed, addr)
self.cpu.assembler.make_sure_mc_exists()
self.cpu.assembler.malloc_func_addr = addr
Modified: pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86.py
==============================================================================
--- pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86.py (original)
+++ pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86.py Wed May 26 19:06:47 2010
@@ -179,6 +179,14 @@
def test_or8_rr():
assert_encodes_as(CodeBuilder32, 'OR8_rr', (bl, bh), '\x08\xFB')
+def test_test8_mi():
+ assert_encodes_as(CodeBuilder32, 'TEST8_mi', ((edx, 16), 99), '\xF6\x42\x10\x63')
+
+def test_mov8():
+ cb = CodeBuilder32
+ assert_encodes_as(cb, 'MOV8_mi', ((edx, 16), 99), '\xC6\x42\x10\x63')
+ assert_encodes_as(cb, 'MOV8_ai', ((ebx, ecx, 2, 16), 99), '\xC6\x44\x8B\x10\x63')
+
class CodeBuilder64(CodeBuilderMixin, X86_64_CodeBuilder):
pass
Modified: pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86_32_auto_encoding.py
==============================================================================
--- pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86_32_auto_encoding.py (original)
+++ pypy/branch/x86-64-jit-backend/pypy/jit/backend/x86/test/test_rx86_32_auto_encoding.py Wed May 26 19:06:47 2010
@@ -229,6 +229,9 @@
# Can't test automatically right now, we don't know
# which register types to use
py.test.skip('Skipping CVT instructions for now')
+ if methname == 'FSTP_b':
+ # Doesn't work on 64-bit, skipping for now
+ py.test.skip('Skipping FSTP')
return [args]
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