[pypy-svn] pypy commit c1dae116dd3e: Make backend translate again
Bitbucket
commits-noreply at bitbucket.org
Mon Dec 13 17:58:21 CET 2010
# HG changeset patch -- Bitbucket.org
# Project pypy
# URL http://bitbucket.org/pypy/pypy/overview
# User David Schneider <david.schneider at picle.org>
# Date 1292254528 0
# Node ID c1dae116dd3ea2d26b66e5324f99029203113ec2
# Parent 4268e926c86c96a08c61a75c483a5fdf71d15e9a
Make backend translate again
--- a/pypy/jit/backend/arm/assembler.py
+++ b/pypy/jit/backend/arm/assembler.py
@@ -393,9 +393,9 @@ class AssemblerARM(ResOpAssembler):
else:
cb.gen_load_int(r.ip.value, n, cond=fcond)
if rev:
- cb.ADD_rr(r.sp.value, base_reg.value, reg.value, cond=fcond)
+ cb.ADD_rr(r.sp.value, base_reg.value, r.ip.value, cond=fcond)
else:
- cb.SUB_rr(r.sp.value, base_reg.value, reg.value, cond=fcond)
+ cb.SUB_rr(r.sp.value, base_reg.value, r.ip.value, cond=fcond)
def _walk_operations(self, operations, regalloc):
fcond=c.AL
@@ -429,7 +429,9 @@ class AssemblerARM(ResOpAssembler):
def assemble_bridge(self, faildescr, inputargs, operations):
self.setup()
self.debug = False
- enc = rffi.cast(rffi.CCHARP, faildescr._failure_recovery_code)
+ code = faildescr._failure_recovery_code
+ assert isinstance(code, int)
+ enc = rffi.cast(rffi.CCHARP, code)
longevity = compute_vars_longevity(inputargs, operations)
regalloc = ARMRegisterManager(longevity, assembler=self, frame_manager=ARMFrameManager())
@@ -522,7 +524,7 @@ class AssemblerARM(ResOpAssembler):
pass
def make_operation_list():
- def notimplemented(self, op, regalloc, fcond):
+ def notimplemented(self, op, arglocs, regalloc, fcond):
raise NotImplementedError, op
operations = [None] * (rop._LAST+1)
@@ -539,7 +541,7 @@ def make_operation_list():
return operations
def make_guard_operation_list():
- def notimplemented(self, op, guard_op, regalloc, fcond):
+ def notimplemented(self, op, guard_op, arglocs, regalloc, fcond):
raise NotImplementedError, op
guard_operations = [notimplemented] * rop._LAST
for key, value in rop.__dict__.items():
--- a/pypy/jit/backend/arm/opassembler.py
+++ b/pypy/jit/backend/arm/opassembler.py
@@ -240,8 +240,9 @@ class OpAssembler(object):
return fcond
def emit_op_call(self, op, args, regalloc, fcond, spill_all_regs=False):
- adr = args[0]
- cond = self._emit_call(adr, op.getarglist()[1:], regalloc, fcond,
+ adr = args[0].value
+ arglist = op.getarglist()[1:]
+ cond = self._emit_call(adr, arglist, regalloc, fcond,
op.result, spill_all_regs=spill_all_regs)
descr = op.getdescr()
#XXX Hack, Hack, Hack
@@ -312,10 +313,6 @@ class OpAssembler(object):
self.mc.MOV_rr(resloc.value, argloc.value)
return fcond
- def emit_op_cond_call_gc_wb(self, op, regalloc, fcond):
- #XXX implement once gc support is in place
- return fcond
-
def emit_op_guard_no_exception(self, op, arglocs, regalloc, fcond):
loc = arglocs[0]
failargs = arglocs[1:]
@@ -340,9 +337,10 @@ class OpAssembler(object):
self.mc.STR_ri(r.ip.value, loc1.value)
return fcond
- def emit_op_debug_merge_point(self, op, regalloc, fcond):
+ def emit_op_debug_merge_point(self, op, arglocs, regalloc, fcond):
return fcond
emit_op_jit_debug = emit_op_debug_merge_point
+ emit_op_cond_call_gc_wb = emit_op_debug_merge_point
class FieldOpAssembler(object):
@@ -753,22 +751,11 @@ class AllocOpAssembler(object):
result=result)
def emit_op_new(self, op, arglocs, regalloc, fcond):
- self._emit_call(self.malloc_func_addr, arglocs,
- regalloc, result=op.result)
- #XXX free args here, because _emit_call works on regalloc
- regalloc.possibly_free_vars(arglocs)
- regalloc.possibly_free_var(op.result)
return fcond
def emit_op_new_with_vtable(self, op, arglocs, regalloc, fcond):
- classint = arglocs[-1].value
- callargs = arglocs[:-1]
- self._emit_call(self.malloc_func_addr, callargs,
- regalloc, result=op.result)
+ classint = arglocs[0].value
self.set_vtable(op.result, classint)
- #XXX free args here, because _emit_call works on regalloc
- regalloc.possibly_free_vars(callargs)
- regalloc.possibly_free_var(op.result)
return fcond
def set_vtable(self, box, vtable):
--- a/pypy/jit/backend/arm/codebuilder.py
+++ b/pypy/jit/backend/arm/codebuilder.py
@@ -121,12 +121,12 @@ class AbstractARMv7Builder(object):
return self._pos
size_of_gen_load_int = 4 * WORD
- #XXX use MOV_ri if value fits in imm
+ ofs_shift = zip(range(8, 25, 8), range(12, 0, -4))
def gen_load_int(self, r, value, cond=cond.AL):
"""r is the register number, value is the value to be loaded to the
register"""
self.MOV_ri(r, (value & 0xFF), cond=cond)
- for offset, shift in zip(range(8, 25, 8), range(12, 0, -4)):
+ for offset, shift in self.ofs_shift:
b = (value >> offset) & 0xFF
if b == 0:
continue
--- a/pypy/jit/backend/arm/regalloc.py
+++ b/pypy/jit/backend/arm/regalloc.py
@@ -14,6 +14,7 @@ from pypy.jit.backend.llsupport.descr im
from pypy.jit.backend.llsupport import symbolic
from pypy.rpython.lltypesystem import lltype, rffi, rstr, llmemory
from pypy.jit.codewriter import heaptracker
+from pypy.rlib.objectmodel import we_are_translated
class TempInt(TempBox):
type = INT
@@ -86,7 +87,10 @@ class ARMRegisterManager(RegisterManager
del self.reg_bindings[var]
self.free_regs.append(loc)
except KeyError:
- import pdb; pdb.set_trace()
+ if not we_are_translated():
+ import pdb; pdb.set_trace()
+ else:
+ raise ValueError
def _check_imm_arg(self, arg, size=0xFF, allow_zero=True):
if isinstance(arg, ConstInt):
@@ -244,7 +248,7 @@ class ARMRegisterManager(RegisterManager
prepare_op_int_invert = prepare_op_int_neg
def prepare_op_call(self, op, fcond):
- args = [rffi.cast(lltype.Signed, op.getarg(0).getint())]
+ args = [imm(rffi.cast(lltype.Signed, op.getarg(0).getint()))]
return args
def _prepare_guard(self, op, args=None):
@@ -309,7 +313,7 @@ class ARMRegisterManager(RegisterManager
boxes.append(box)
if op.result in self.longevity:
resloc = self.force_allocate_reg(op.result, boxes)
- boxes.append(resloc)
+ boxes.append(op.result)
else:
resloc = None
pos_exc_value = imm(self.assembler.cpu.pos_exc_value())
@@ -555,17 +559,21 @@ class ARMRegisterManager(RegisterManager
def prepare_op_new(self, op, fcond):
arglocs = self._prepare_args_for_new_op(op.getdescr())
- #XXX args are freed in assembler._emit_call
- #self.possibly_free_vars(arglocs)
+ self.assembler._emit_call(self.assembler.malloc_func_addr,
+ arglocs, self, result=op.result)
+ self.possibly_free_vars(arglocs)
self.possibly_free_var(op.result)
- return arglocs
+ return []
def prepare_op_new_with_vtable(self, op, fcond):
classint = op.getarg(0).getint()
descrsize = heaptracker.vtable2descr(self.assembler.cpu, classint)
- arglocs = self._prepare_args_for_new_op(descrsize)
- arglocs.append(imm(classint))
- return arglocs
+ callargs = self._prepare_args_for_new_op(descrsize)
+ self.assembler._emit_call(self.assembler.malloc_func_addr,
+ callargs, self, result=op.result)
+ self.possibly_free_vars(callargs)
+ self.possibly_free_var(op.result)
+ return [imm(classint)]
def prepare_op_new_array(self, op, fcond):
gc_ll_descr = self.assembler.cpu.gc_ll_descr
@@ -634,7 +642,7 @@ class ARMRegisterManager(RegisterManager
faildescr = guard_op.getdescr()
fail_index = self.assembler.cpu.get_fail_descr_number(faildescr)
self.assembler._write_fail_index(fail_index)
- args = [rffi.cast(lltype.Signed, op.getarg(0).getint())]
+ args = [imm(rffi.cast(lltype.Signed, op.getarg(0).getint()))]
# force all reg values to be spilled when calling
self.assembler.emit_op_call(op, args, self, fcond, spill_all_regs=True)
@@ -644,6 +652,7 @@ class ARMRegisterManager(RegisterManager
faildescr = guard_op.getdescr()
fail_index = self.assembler.cpu.get_fail_descr_number(faildescr)
self.assembler._write_fail_index(fail_index)
+ return []
def _prepare_args_for_new_op(self, new_args):
gc_ll_descr = self.assembler.cpu.gc_ll_descr
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