[pypy-svn] r79795 - in pypy/branch/arm-backend/pypy/jit/backend/arm: . test
david at codespeak.net
david at codespeak.net
Sat Dec 4 09:25:22 CET 2010
Author: david
Date: Sat Dec 4 09:25:20 2010
New Revision: 79795
Modified:
pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py
pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py
pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_generated.py
pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_zll_random.py
Log:
Fixes for getfield, setfield and for rshift operations with constant arguments
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/assembler.py Sat Dec 4 09:25:20 2010
@@ -5,8 +5,9 @@
from pypy.jit.backend.arm.codebuilder import ARMv7Builder, ARMv7InMemoryBuilder
from pypy.jit.backend.arm.regalloc import ARMRegisterManager, ARMFrameManager
from pypy.jit.backend.llsupport.regalloc import compute_vars_longevity, TempBox
-from pypy.jit.metainterp.history import (Const, ConstInt, BoxInt, AbstractFailDescr,
- INT, REF, FLOAT)
+from pypy.jit.metainterp.history import (Const, ConstInt, ConstPtr,
+ BoxInt, BoxPtr, AbstractFailDescr,
+ INT, REF, FLOAT)
from pypy.jit.metainterp.resoperation import rop
from pypy.rlib import rgc
from pypy.rpython.annlowlevel import llhelper
@@ -454,6 +455,8 @@
if isinstance(thing, Const):
if isinstance(thing, ConstInt):
box = BoxInt()
+ elif isinstance(thing, ConstPtr):
+ box = BoxPtr()
else:
box = TempBox()
loc = regalloc.force_allocate_reg(box,
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/opassembler.py Sat Dec 4 09:25:20 2010
@@ -146,8 +146,8 @@
emit_op_int_or = gen_emit_op_ri('ORR')
emit_op_int_xor = gen_emit_op_ri('EOR')
emit_op_int_lshift = gen_emit_op_ri('LSL', imm_size=0x1F, allow_zero=False, commutative=False)
- emit_op_int_rshift = gen_emit_op_ri('ASR', imm_size=0x1F, commutative=False)
- emit_op_uint_rshift = gen_emit_op_ri('LSR', imm_size=0x1F, commutative=False)
+ emit_op_int_rshift = gen_emit_op_ri('ASR', imm_size=0x1F, allow_zero=False, commutative=False)
+ emit_op_uint_rshift = gen_emit_op_ri('LSR', imm_size=0x1F, allow_zero=False, commutative=False)
emit_op_int_lt = gen_emit_cmp_op(c.LT)
emit_op_int_le = gen_emit_cmp_op(c.LE)
@@ -444,13 +444,16 @@
_mixin_ = True
def emit_op_setfield_gc(self, op, regalloc, fcond):
- a0 = op.getarg(0)
- a1 = op.getarg(1)
+ boxes = list(op.getarglist())
+ a0, a1 = boxes
ofs, size, ptr = self._unpack_fielddescr(op.getdescr())
#ofs_loc = regalloc.make_sure_var_in_reg(ConstInt(ofs))
#size_loc = regalloc.make_sure_var_in_reg(ofs)
- base_loc = regalloc.make_sure_var_in_reg(a0, imm_fine=False)
- value_loc = regalloc.make_sure_var_in_reg(a1, [a0], imm_fine=False)
+ base_loc, base_box = self._ensure_value_is_boxed(a0, regalloc, boxes)
+ boxes.append(base_box)
+ value_loc, value_box = self._ensure_value_is_boxed(a1, regalloc, boxes)
+ boxes.append(value_box)
+ regalloc.possibly_free_vars(boxes)
if size == 4:
self.mc.STR_ri(value_loc.value, base_loc.value, ofs)
elif size == 2:
@@ -467,8 +470,12 @@
a0 = op.getarg(0)
ofs, size, ptr = self._unpack_fielddescr(op.getdescr())
# ofs_loc = regalloc.make_sure_var_in_reg(ConstInt(ofs))
- base_loc = regalloc.make_sure_var_in_reg(a0, imm_fine=False)
+ base_loc, base_box = self._ensure_value_is_boxed(a0, regalloc)
res = regalloc.force_allocate_reg(op.result, [a0])
+ regalloc.possibly_free_var(a0)
+ regalloc.possibly_free_var(base_box)
+ regalloc.possibly_free_var(op.result)
+
if size == 4:
self.mc.LDR_ri(res.value, base_loc.value, ofs)
elif size == 2:
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_generated.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_generated.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_generated.py Sat Dec 4 09:25:20 2010
@@ -555,3 +555,59 @@
assert cpu.get_latest_value_int(3) == 357913940
assert cpu.get_latest_value_int(4) == 16
assert cpu.get_latest_value_int(5) == -5
+
+ def test_wrong_result2(self):
+ # block length 10
+ # random seed 1
+ f1 = BasicFailDescr(1)
+ f2 = BasicFailDescr(2)
+ f3 = BasicFailDescr(3)
+ v1 = BoxInt()
+ v2 = BoxInt()
+ v3 = BoxInt()
+ v4 = BoxInt()
+ v5 = BoxInt()
+ v6 = BoxInt()
+ v7 = BoxInt()
+ v8 = BoxInt()
+ v9 = BoxInt()
+ v10 = BoxInt()
+ v11 = BoxInt()
+ v12 = BoxInt()
+ v13 = BoxInt()
+ v14 = BoxInt()
+ v15 = BoxInt()
+ cpu = CPU(None, None)
+ inputargs = [v1, v2, v3, v4, v5, v6, v7, v8, v9, v10]
+ operations = [
+ ResOperation(rop.INT_LE, [v6, v1], v11),
+ ResOperation(rop.SAME_AS, [ConstInt(-14)], v12),
+ ResOperation(rop.INT_ADD, [ConstInt(24), v4], v13),
+ ResOperation(rop.UINT_RSHIFT, [v6, ConstInt(0)], v14),
+ ResOperation(rop.GUARD_VALUE, [v14, ConstInt(1)], None, descr=f3),
+ ResOperation(rop.INT_MUL, [v13, ConstInt(12)], v15),
+ ResOperation(rop.GUARD_FALSE, [v11], None, descr=f1),
+ ResOperation(rop.FINISH, [v2, v3, v5, v7, v10, v8, v9], None, descr=f2),
+ ]
+ operations[-2].setfailargs([v4, v10, v3, v9, v14, v2])
+ operations[4].setfailargs([v14])
+ looptoken = LoopToken()
+ cpu.compile_loop(inputargs, operations, looptoken)
+ cpu.set_future_value_int(0, 14)
+ cpu.set_future_value_int(1, -20)
+ cpu.set_future_value_int(2, 18)
+ cpu.set_future_value_int(3, -2058005163)
+ cpu.set_future_value_int(4, 6)
+ cpu.set_future_value_int(5, 1)
+ cpu.set_future_value_int(6, -16)
+ cpu.set_future_value_int(7, 11)
+ cpu.set_future_value_int(8, 0)
+ cpu.set_future_value_int(9, 19)
+ op = cpu.execute_token(looptoken)
+ assert op.identifier == 1
+ assert cpu.get_latest_value_int(0) == -2058005163
+ assert cpu.get_latest_value_int(1) == 19
+ assert cpu.get_latest_value_int(2) == 18
+ assert cpu.get_latest_value_int(3) == 0
+ assert cpu.get_latest_value_int(4) == 1
+ assert cpu.get_latest_value_int(5) == -20
Modified: pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_zll_random.py
==============================================================================
--- pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_zll_random.py (original)
+++ pypy/branch/arm-backend/pypy/jit/backend/arm/test/test_zll_random.py Sat Dec 4 09:25:20 2010
@@ -9,12 +9,12 @@
# one
OPERATIONS = test_random.OPERATIONS[:]
-#for i in range(4): # make more common
-# OPERATIONS.append(test_ll_random.GetFieldOperation(rop.GETFIELD_GC))
-# OPERATIONS.append(test_ll_random.GetFieldOperation(rop.GETFIELD_GC))
-# OPERATIONS.append(test_ll_random.SetFieldOperation(rop.SETFIELD_GC))
-# #OPERATIONS.append(test_ll_random.NewOperation(rop.NEW))
-# #OPERATIONS.append(test_ll_random.NewOperation(rop.NEW_WITH_VTABLE))
+for i in range(4): # make more common
+ OPERATIONS.append(test_ll_random.GetFieldOperation(rop.GETFIELD_GC))
+ OPERATIONS.append(test_ll_random.GetFieldOperation(rop.GETFIELD_GC))
+ OPERATIONS.append(test_ll_random.SetFieldOperation(rop.SETFIELD_GC))
+ OPERATIONS.append(test_ll_random.NewOperation(rop.NEW))
+ OPERATIONS.append(test_ll_random.NewOperation(rop.NEW_WITH_VTABLE))
#
# OPERATIONS.append(test_ll_random.GetArrayItemOperation(rop.GETARRAYITEM_GC))
# OPERATIONS.append(test_ll_random.GetArrayItemOperation(rop.GETARRAYITEM_GC))
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