[pypy-svn] r37592 - in pypy/dist/pypy/jit/codegen: demo ppc test
mwh at codespeak.net
mwh at codespeak.net
Tue Jan 30 14:09:11 CET 2007
Author: mwh
Date: Tue Jan 30 14:09:10 2007
New Revision: 37592
Modified:
pypy/dist/pypy/jit/codegen/demo/rerun_failures.py
pypy/dist/pypy/jit/codegen/ppc/instruction.py
pypy/dist/pypy/jit/codegen/ppc/regalloc.py
pypy/dist/pypy/jit/codegen/test/rgenop_tests.py
Log:
random-tester inspired fixes to the tracking of which bits in a condition
register field are of interest as results of comparisons are spilled and
unspilled.
Modified: pypy/dist/pypy/jit/codegen/demo/rerun_failures.py
==============================================================================
--- pypy/dist/pypy/jit/codegen/demo/rerun_failures.py (original)
+++ pypy/dist/pypy/jit/codegen/demo/rerun_failures.py Tue Jan 30 14:09:10 2007
@@ -22,6 +22,7 @@
def test_2871_1_100(): rerun(2871, 1, 100)
def test_6294(): rerun(6294)
-# here's a ppcfew failure:
+# here's a ppcfew failure or two:
def test_39263(): rerun(39263)
+def test_33851(): rerun(33851)
Modified: pypy/dist/pypy/jit/codegen/ppc/instruction.py
==============================================================================
--- pypy/dist/pypy/jit/codegen/ppc/instruction.py (original)
+++ pypy/dist/pypy/jit/codegen/ppc/instruction.py Tue Jan 30 14:09:10 2007
@@ -438,6 +438,7 @@
self.targetbuilder = targetbuilder
def allocate(self, allocator):
self.crf = allocator.loc_of(self.reg_args[0])
+ assert self.crf.info[0] != -1
assert self.targetbuilder.initial_var2loc is None
self.targetbuilder.initial_var2loc = {}
@@ -465,6 +466,7 @@
asm.load_word(rSCRATCH, 0)
asm.mtctr(rSCRATCH)
bit, negated = self.crf.info
+ assert bit != -1
if negated ^ self.jump_if_true:
BO = 12 # jump if relavent bit is set in the CR
else:
@@ -626,6 +628,11 @@
self.var = var
self.reg = reg
self.stack = stack
+ if not isinstance(self.reg, GPR):
+ assert isinstance(self.reg, CRF)
+ self.moveinsn = self.reg.move_from_gpr(None, 0)
+ else:
+ self.moveinsn = None
def __repr__(self):
return '<Spill-%d %s: %s, %s>'%(self._magic_index, self.var, self.reg, self.stack)
def emit(self, asm):
@@ -634,9 +641,8 @@
else:
r = 0
asm.lwz(r, rFP, self.stack.offset)
- if not isinstance(self.reg, GPR):
- assert isinstance(self.reg, CRF)
- self.reg.move_from_gpr(None, 0).emit(asm)
+ if self.moveinsn:
+ self.moveinsn.emit(asm)
class Spill(AllocTimeInsn):
""" A special instruction inserted by our register "allocator."
Modified: pypy/dist/pypy/jit/codegen/ppc/regalloc.py
==============================================================================
--- pypy/dist/pypy/jit/codegen/ppc/regalloc.py (original)
+++ pypy/dist/pypy/jit/codegen/ppc/regalloc.py Tue Jan 30 14:09:10 2007
@@ -102,10 +102,11 @@
self.spill(reg, argtospill)
if DEBUG_PRINT:
- print "allocate_reg: Spilled %r to %r." % (argtospill, self.loc_of(argtospill))
+ print "allocate_reg: Spilled %r from %r to %r." % (argtospill, reg, self.loc_of(argtospill))
# update data structures to put newarg into the register
- self.set(newarg, reg.alloc.make_loc())
+ reg = reg.alloc.make_loc()
+ self.set(newarg, reg)
if DEBUG_PRINT:
print "allocate_reg: Put %r in stolen reg %r." % (newarg, reg)
return reg
@@ -140,17 +141,15 @@
if DEBUG_PRINT:
print "Processing instruction"
print insn
- #print "with args", insn.reg_args, "and result", insn.result, ":"
-
- #print "LRU list was:", self.lru
+ print "LRU list was:", self.lru
# put things into the lru
for arg in insn.reg_args:
self._promote(arg)
if insn.result:
self._promote(insn.result)
- #if DEBUG_PRINT:
- # print "LRU list is now:", self.lru
+ if DEBUG_PRINT:
+ print "LRU list is now:", self.lru
# We need to allocate a register for each used
# argument that is not already in one
Modified: pypy/dist/pypy/jit/codegen/test/rgenop_tests.py
==============================================================================
--- pypy/dist/pypy/jit/codegen/test/rgenop_tests.py (original)
+++ pypy/dist/pypy/jit/codegen/test/rgenop_tests.py Tue Jan 30 14:09:10 2007
@@ -1384,3 +1384,53 @@
res = fnptr(1, -58, -50)
assert res == 1424339776
+
+ def test_from_random_2_direct(self):
+
+ # def dummyfn(counter, d, e):
+ # a = not d
+ # while counter:
+ # d = a and e
+ # counter -= 1
+ # return intmask(d)
+
+ rgenop = self.RGenOp()
+ signed_kind = rgenop.kindToken(lltype.Signed)
+ bool_kind = rgenop.kindToken(lltype.Bool)
+
+ builder0, gv_callable, [v0, v1, v2] = rgenop.newgraph(rgenop.sigToken(FUNC3), 'compiled_dummyfn')
+ builder0.start_writing()
+ v3 = builder0.genop1('int_is_true', v1)
+
+ builder1 = builder0.jump_if_true(v3, [v0, v1, v2])
+
+ args_gv = [v0, v1, v2, rgenop.genconst(1)]
+ label0 = builder0.enter_next_block([signed_kind, signed_kind, signed_kind, bool_kind], args_gv)
+ [v4, v5, v6, v7] = args_gv
+
+ v8 = builder0.genop1('int_is_true', v4)
+ builder2 = builder0.jump_if_false(v8, [v5])
+ builder3 = builder0.jump_if_false(v7, [v7, v6, v4])
+
+ args_gv = [v6, v6, v7, v4]
+ label1 = builder0.enter_next_block([signed_kind, signed_kind, bool_kind, signed_kind], args_gv)
+ [v9, v10, v11, v12] = args_gv
+
+ v13 = builder0.genop2('int_sub', v12, rgenop.genconst(1))
+ builder0.finish_and_goto([v13, v9, v10, v11], label0)
+
+ builder1.start_writing()
+ builder1.finish_and_goto([v0, v1, v2, rgenop.genconst(0)], label0)
+
+ builder3.start_writing()
+ v14 = builder3.genop1('cast_bool_to_int', v7)
+ builder3.finish_and_goto([v14, v6, v7, v4], label1)
+
+ builder2.start_writing()
+ builder2.finish_and_return(rgenop.sigToken(FUNC3), v5)
+ builder2.end()
+
+ fnptr = self.cast(gv_callable, 3)
+
+ res = fnptr(2, -89, -99)
+ assert res == 0
More information about the Pypy-commit
mailing list