[Baypiggies] Guido's Blog: It isn't Easy to Remove the GIL

[Andy Wiggin]

> Ignoring threshold effects (a huge assumption), joint reductions in voltage
> and frequency yield a 3rd order (X**3) reduction in power.

The example I'm looking at, the chip vendor reduces core vdd by 10%
(1.2 -> 1.09) and core clock frequency by 30% (3.0GHz -> 2.3GHz) and
this cuts power by 50%. This allows them to put two of these things
(in essence, at least) in one package because there within the thermal
budget.

So you can get 2 cores at 3GHz or 4 cores at 2.3GHz, for roughly the
same price I am told. The vendor claims a 70% increase in peak flops
for the 4 core version.

Ignoring the vdd scaling (since basically no one cares about core vdd
when they're buying CPUs), this seems non-linear to me because you
give up 30% in CPU frequency and get 50% in power savings.

I'm guessing that your assumptions are more in terms of moving from
one process node to  the next, whereas the example I'm looking at (I'm
pretty sure) is based on two thermally bound designs at the same
process node. Also, within one process node, I believe the opportunity
for voltage scaling is limited, so I don't believe you can freely
scale it the way you can freely scale (down, at least) clock speed.

Regards,
Andy